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Commit a19ba362 authored by Arun KS's avatar Arun KS
Browse files

clk: qcom: clock-gcc-8952: Vote for CX when gpll3 & 4 in use 



To run at gpll3 and gpll4 at vco mode 0, Cx must be at NOM
voltage. Vote for cx NOM when plls are in use.

Change-Id: Ia6614c48a1cc46e7d7630ded5b1d5f27755c83ec
Signed-off-by: default avatarArun KS <arunks@codeaurora.org>
parent cdecac51

drivers/clk/msm/clock-gcc-8952.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -474,6 +474,7 @@ static struct alpha_pll_clk gpll3_clk_src = { 
		.parent = &xo_clk_src.c,

		.parent = &xo_clk_src.c,

		.dbg_name = "gpll3_clk_src",

		.dbg_name = "gpll3_clk_src",

		.ops = &clk_ops_dyna_alpha_pll,

		.ops = &clk_ops_dyna_alpha_pll,

		VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),

		CLK_INIT(gpll3_clk_src.c),

		CLK_INIT(gpll3_clk_src.c),

	},

	},

};

};
@@ -489,6 +490,7 @@ static struct pll_vote_clk gpll4_clk_src = { 
		.parent = &xo_clk_src.c,

		.parent = &xo_clk_src.c,

		.dbg_name = "gpll4_clk_src",

		.dbg_name = "gpll4_clk_src",

		.ops = &clk_ops_pll_vote,

		.ops = &clk_ops_pll_vote,

		VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),

		CLK_INIT(gpll4_clk_src.c),

		CLK_INIT(gpll4_clk_src.c),

	},

	},

};

};