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Commit a0edcdbe authored by Govindraj.R's avatar Govindraj.R Committed by Kevin Hilman
Browse files

OMAP clock: Add uart4_ick/fck definitions for 3630 



This is only valid for omap 36xx family of chips.

Signed-off-by: default avatarSergio Aguirre <saaguirre@ti.com>
Signed-off-by: default avatarGovindraj.R <govindraj.raja@ti.com>
Acked-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
parent 8da37d9d

arch/arm/mach-omap2/clock3xxx_data.c

+22 −0
Original line number Diff line number Diff line
@@ -2465,6 +2465,16 @@ static struct clk uart3_fck = { 
	.recalc		= &followparent_recalc,

};



static struct clk uart4_fck = {

	.name		= "uart4_fck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &per_48m_fck,

	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),

	.enable_bit	= OMAP3630_EN_UART4_SHIFT,

	.clkdm_name	= "per_clkdm",

	.recalc		= &followparent_recalc,

};



static struct clk gpt2_fck = {

	.name		= "gpt2_fck",

	.ops		= &clkops_omap2_dflt_wait,
@@ -2715,6 +2725,16 @@ static struct clk uart3_ick = { 
	.recalc		= &followparent_recalc,

};



static struct clk uart4_ick = {

	.name		= "uart4_ick",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &per_l4_ick,

	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),

	.enable_bit	= OMAP3630_EN_UART4_SHIFT,

	.clkdm_name	= "per_clkdm",

	.recalc		= &followparent_recalc,

};



static struct clk gpt9_ick = {

	.name		= "gpt9_ick",

	.ops		= &clkops_omap2_dflt_wait,
@@ -3349,6 +3369,7 @@ static struct omap_clk omap3xxx_clks[] = { 
	CLK(NULL,	"per_96m_fck",	&per_96m_fck,	CK_3XXX),

	CLK(NULL,	"per_48m_fck",	&per_48m_fck,	CK_3XXX),

	CLK(NULL,	"uart3_fck",	&uart3_fck,	CK_3XXX),

	CLK(NULL,	"uart4_fck",	&uart4_fck,	CK_36XX),

	CLK(NULL,	"gpt2_fck",	&gpt2_fck,	CK_3XXX),

	CLK(NULL,	"gpt3_fck",	&gpt3_fck,	CK_3XXX),

	CLK(NULL,	"gpt4_fck",	&gpt4_fck,	CK_3XXX),
@@ -3372,6 +3393,7 @@ static struct omap_clk omap3xxx_clks[] = { 
	CLK(NULL,	"gpio2_ick",	&gpio2_ick,	CK_3XXX),

	CLK(NULL,	"wdt3_ick",	&wdt3_ick,	CK_3XXX),

	CLK(NULL,	"uart3_ick",	&uart3_ick,	CK_3XXX),

	CLK(NULL,	"uart4_ick",	&uart4_ick,	CK_36XX),

	CLK(NULL,	"gpt9_ick",	&gpt9_ick,	CK_3XXX),

	CLK(NULL,	"gpt8_ick",	&gpt8_ick,	CK_3XXX),

	CLK(NULL,	"gpt7_ick",	&gpt7_ick,	CK_3XXX),