Loading drivers/net/wireless/ath/ath5k/eeprom.c +2 −2 Original line number Diff line number Diff line Loading @@ -429,8 +429,8 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset, ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; AR5K_EEPROM_READ(o++, val); ee->ee_i_cal[mode] = (val >> 8) & 0x3f; ee->ee_q_cal[mode] = (val >> 3) & 0x1f; ee->ee_i_cal[mode] = (val >> 5) & 0x3f; ee->ee_q_cal[mode] = val & 0x1f; if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { AR5K_EEPROM_READ(o++, val); Loading drivers/net/wireless/ath/ath5k/phy.c +21 −20 Original line number Diff line number Diff line Loading @@ -1386,38 +1386,39 @@ static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, goto done; /* Calibration has finished, get the results and re-run */ /* work around empty results which can apparently happen on 5212 */ for (i = 0; i <= 10; i++) { iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); if (i_pwr && q_pwr) break; } i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; q_coffd = q_pwr >> 7; /* No correction */ if (i_coffd == 0 || q_coffd == 0) /* protect against divide by 0 and loss of sign bits */ if (i_coffd == 0 || q_coffd < 2) goto done; i_coff = ((-iq_corr) / i_coffd); /* Boundary check */ if (i_coff > 31) i_coff = 31; if (i_coff < -32) i_coff = -32; i_coff = (-iq_corr) / i_coffd; i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ q_coff = (((s32)i_pwr / q_coffd) - 128); q_coff = (i_pwr / q_coffd) - 128; q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ /* Boundary check */ if (q_coff > 15) q_coff = 15; if (q_coff < -16) q_coff = -16; ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", i_coff, q_coff, i_coffd, q_coffd); /* Commit new I/Q value */ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); /* Commit new I/Q values (set enable bit last to match HAL sources) */ AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); /* Re-enable calibration -if we don't we'll commit * the same values again and again */ Loading Loading @@ -1873,7 +1874,7 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) break; case AR5K_ANTMODE_FIXED_A: def_ant = 1; tx_ant = 0; tx_ant = 1; use_def_for_tx = true; update_def_on_tx = false; use_def_for_rts = true; Loading @@ -1882,7 +1883,7 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) break; case AR5K_ANTMODE_FIXED_B: def_ant = 2; tx_ant = 0; tx_ant = 2; use_def_for_tx = true; update_def_on_tx = false; use_def_for_rts = true; Loading drivers/net/wireless/ath/ath5k/reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -2187,6 +2187,7 @@ */ #define AR5K_PHY_IQ 0x9920 /* Register Address */ #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ #define AR5K_PHY_IQ_CORR_Q_Q_COFF_S 0 #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ Loading drivers/net/wireless/ath/ath5k/reset.c +12 −10 Original line number Diff line number Diff line Loading @@ -851,12 +851,15 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, AR5K_INIT_CYCRSSI_THR1); /* I/Q correction * TODO: Per channel i/q infos ? */ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | /* I/Q correction (set enable bit last to match HAL sources) */ /* TODO: Per channel i/q infos ? */ if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, ee->ee_i_cal[ee_mode]); AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, ee->ee_q_cal[ee_mode]); AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); } /* Heavy clipping -disable for now */ if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1) Loading Loading @@ -1379,11 +1382,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, ath5k_hw_set_sleep_clock(ah, true); /* * Disable beacons and reset the register * Disable beacons and reset the TSF */ AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE); ath5k_hw_reset_tsf(ah); return 0; } Loading drivers/net/wireless/ipw2x00/ipw2200.c +17 −2 Original line number Diff line number Diff line Loading @@ -3177,14 +3177,27 @@ static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len) int total_nr = 0; int i; struct pci_pool *pool; u32 *virts[CB_NUMBER_OF_ELEMENTS_SMALL]; dma_addr_t phys[CB_NUMBER_OF_ELEMENTS_SMALL]; void **virts; dma_addr_t *phys; IPW_DEBUG_TRACE("<< : \n"); virts = kmalloc(sizeof(void *) * CB_NUMBER_OF_ELEMENTS_SMALL, GFP_KERNEL); if (!virts) return -ENOMEM; phys = kmalloc(sizeof(dma_addr_t) * CB_NUMBER_OF_ELEMENTS_SMALL, GFP_KERNEL); if (!phys) { kfree(virts); return -ENOMEM; } pool = pci_pool_create("ipw2200", priv->pci_dev, CB_MAX_LENGTH, 0, 0); if (!pool) { IPW_ERROR("pci_pool_create failed\n"); kfree(phys); kfree(virts); return -ENOMEM; } Loading Loading @@ -3254,6 +3267,8 @@ static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len) pci_pool_free(pool, virts[i], phys[i]); pci_pool_destroy(pool); kfree(phys); kfree(virts); return ret; } Loading Loading
drivers/net/wireless/ath/ath5k/eeprom.c +2 −2 Original line number Diff line number Diff line Loading @@ -429,8 +429,8 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset, ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; AR5K_EEPROM_READ(o++, val); ee->ee_i_cal[mode] = (val >> 8) & 0x3f; ee->ee_q_cal[mode] = (val >> 3) & 0x1f; ee->ee_i_cal[mode] = (val >> 5) & 0x3f; ee->ee_q_cal[mode] = val & 0x1f; if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { AR5K_EEPROM_READ(o++, val); Loading
drivers/net/wireless/ath/ath5k/phy.c +21 −20 Original line number Diff line number Diff line Loading @@ -1386,38 +1386,39 @@ static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, goto done; /* Calibration has finished, get the results and re-run */ /* work around empty results which can apparently happen on 5212 */ for (i = 0; i <= 10; i++) { iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); if (i_pwr && q_pwr) break; } i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; q_coffd = q_pwr >> 7; /* No correction */ if (i_coffd == 0 || q_coffd == 0) /* protect against divide by 0 and loss of sign bits */ if (i_coffd == 0 || q_coffd < 2) goto done; i_coff = ((-iq_corr) / i_coffd); /* Boundary check */ if (i_coff > 31) i_coff = 31; if (i_coff < -32) i_coff = -32; i_coff = (-iq_corr) / i_coffd; i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ q_coff = (((s32)i_pwr / q_coffd) - 128); q_coff = (i_pwr / q_coffd) - 128; q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ /* Boundary check */ if (q_coff > 15) q_coff = 15; if (q_coff < -16) q_coff = -16; ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", i_coff, q_coff, i_coffd, q_coffd); /* Commit new I/Q value */ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); /* Commit new I/Q values (set enable bit last to match HAL sources) */ AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); /* Re-enable calibration -if we don't we'll commit * the same values again and again */ Loading Loading @@ -1873,7 +1874,7 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) break; case AR5K_ANTMODE_FIXED_A: def_ant = 1; tx_ant = 0; tx_ant = 1; use_def_for_tx = true; update_def_on_tx = false; use_def_for_rts = true; Loading @@ -1882,7 +1883,7 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) break; case AR5K_ANTMODE_FIXED_B: def_ant = 2; tx_ant = 0; tx_ant = 2; use_def_for_tx = true; update_def_on_tx = false; use_def_for_rts = true; Loading
drivers/net/wireless/ath/ath5k/reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -2187,6 +2187,7 @@ */ #define AR5K_PHY_IQ 0x9920 /* Register Address */ #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ #define AR5K_PHY_IQ_CORR_Q_Q_COFF_S 0 #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ Loading
drivers/net/wireless/ath/ath5k/reset.c +12 −10 Original line number Diff line number Diff line Loading @@ -851,12 +851,15 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, AR5K_INIT_CYCRSSI_THR1); /* I/Q correction * TODO: Per channel i/q infos ? */ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) | /* I/Q correction (set enable bit last to match HAL sources) */ /* TODO: Per channel i/q infos ? */ if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, ee->ee_i_cal[ee_mode]); AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, ee->ee_q_cal[ee_mode]); AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); } /* Heavy clipping -disable for now */ if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1) Loading Loading @@ -1379,11 +1382,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, ath5k_hw_set_sleep_clock(ah, true); /* * Disable beacons and reset the register * Disable beacons and reset the TSF */ AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE | AR5K_BEACON_RESET_TSF); AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE); ath5k_hw_reset_tsf(ah); return 0; } Loading
drivers/net/wireless/ipw2x00/ipw2200.c +17 −2 Original line number Diff line number Diff line Loading @@ -3177,14 +3177,27 @@ static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len) int total_nr = 0; int i; struct pci_pool *pool; u32 *virts[CB_NUMBER_OF_ELEMENTS_SMALL]; dma_addr_t phys[CB_NUMBER_OF_ELEMENTS_SMALL]; void **virts; dma_addr_t *phys; IPW_DEBUG_TRACE("<< : \n"); virts = kmalloc(sizeof(void *) * CB_NUMBER_OF_ELEMENTS_SMALL, GFP_KERNEL); if (!virts) return -ENOMEM; phys = kmalloc(sizeof(dma_addr_t) * CB_NUMBER_OF_ELEMENTS_SMALL, GFP_KERNEL); if (!phys) { kfree(virts); return -ENOMEM; } pool = pci_pool_create("ipw2200", priv->pci_dev, CB_MAX_LENGTH, 0, 0); if (!pool) { IPW_ERROR("pci_pool_create failed\n"); kfree(phys); kfree(virts); return -ENOMEM; } Loading Loading @@ -3254,6 +3267,8 @@ static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len) pci_pool_free(pool, virts[i], phys[i]); pci_pool_destroy(pool); kfree(phys); kfree(virts); return ret; } Loading