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Commit 9ff49ec7 authored by Emilio López's avatar Emilio López Committed by Maxime Ripard
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arm: sunxi: use the right clock phandles for UARTs



All the UARTs are connected to clock gates; now that our clock driver
is able to handle them, make the switch.

Signed-off-by: default avatarEmilio López <emilio@elopez.com.ar>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 07c60ef7
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+6 −6
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

@@ -64,7 +64,7 @@
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

@@ -74,7 +74,7 @@
			interrupts = <17>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

@@ -84,7 +84,7 @@
			interrupts = <18>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

@@ -94,7 +94,7 @@
			interrupts = <19>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

@@ -104,7 +104,7 @@
			interrupts = <20>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};
	};
+2 −2
Original line number Diff line number Diff line
@@ -191,7 +191,7 @@
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

@@ -201,7 +201,7 @@
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};
	};