arm/imx6q: add core drivers clock, gpc, mmdc and src (9fbbe689) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/mach-imx/Kconfig

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		config IMX_HAVE_DMA_V1
		bool

		config HAVE_IMX_GPC
		bool

		config HAVE_IMX_MMDC
		bool

		config HAVE_IMX_SRC
		bool

		#
		# ARCH_MX31 and ARCH_MX35 are left for compatibility
		# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
		@@ -601,6 +611,9 @@ config SOC_IMX6Q
		select ARM_GIC
		select CACHE_L2X0
		select CPU_V7
		select HAVE_IMX_GPC
		select HAVE_IMX_MMDC
		select HAVE_IMX_SRC
		select USE_OF

		help

arch/arm/mach-imx/Makefile

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		@@ -62,3 +62,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
		obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o

		obj-$(CONFIG_DEBUG_LL) += lluart.o
		obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
		obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
		obj-$(CONFIG_HAVE_IMX_SRC) += src.o
		obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o

arch/arm/mach-imx/clock-imx6q.c

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File added.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-imx/gpc.c

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		/*
		* Copyright 2011 Freescale Semiconductor, Inc.
		* Copyright 2011 Linaro Ltd.
		*
		* The code contained herein is licensed under the GNU General Public
		* License. You may obtain a copy of the GNU General Public License
		* Version 2 or later at the following locations:
		*
		* http://www.opensource.org/licenses/gpl-license.html
		* http://www.gnu.org/copyleft/gpl.html
		*/

		#include <linux/io.h>
		#include <linux/irq.h>
		#include <linux/of.h>
		#include <linux/of_address.h>
		#include <linux/of_irq.h>
		#include <asm/hardware/gic.h>

		#define GPC_IMR1 0x008
		#define GPC_PGC_CPU_PDN 0x2a0

		#define IMR_NUM 4

		static void __iomem *gpc_base;
		static u32 gpc_wake_irqs[IMR_NUM];
		static u32 gpc_saved_imrs[IMR_NUM];

		void imx_gpc_pre_suspend(void)
		{
		void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
		int i;

		/* Tell GPC to power off ARM core when suspend */
		writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);

		for (i = 0; i < IMR_NUM; i++) {
		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
		writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
		}
		}

		void imx_gpc_post_resume(void)
		{
		void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
		int i;

		/* Keep ARM core powered on for other low-power modes */
		writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);

		for (i = 0; i < IMR_NUM; i++)
		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
		}

		static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
		{
		unsigned int idx = d->irq / 32 - 1;
		u32 mask;

		/* Sanity check for SPI irq */
		if (d->irq < 32)
		return -EINVAL;

		mask = 1 << d->irq % 32;
		gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] \| mask :
		gpc_wake_irqs[idx] & ~mask;

		return 0;
		}

		static void imx_gpc_irq_unmask(struct irq_data *d)
		{
		void __iomem *reg;
		u32 val;

		/* Sanity check for SPI irq */
		if (d->irq < 32)
		return;

		reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
		val = readl_relaxed(reg);
		val &= ~(1 << d->irq % 32);
		writel_relaxed(val, reg);
		}

		static void imx_gpc_irq_mask(struct irq_data *d)
		{
		void __iomem *reg;
		u32 val;

		/* Sanity check for SPI irq */
		if (d->irq < 32)
		return;

		reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
		val = readl_relaxed(reg);
		val \|= 1 << (d->irq % 32);
		writel_relaxed(val, reg);
		}

		void __init imx_gpc_init(void)
		{
		struct device_node *np;

		np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
		gpc_base = of_iomap(np, 0);
		WARN_ON(!gpc_base);

		/* Register GPC as the secondary interrupt controller behind GIC */
		gic_arch_extn.irq_mask = imx_gpc_irq_mask;
		gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
		gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
		}

arch/arm/mach-imx/mmdc.c

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		/*
		* Copyright 2011 Freescale Semiconductor, Inc.
		* Copyright 2011 Linaro Ltd.
		*
		* The code contained herein is licensed under the GNU General Public
		* License. You may obtain a copy of the GNU General Public License
		* Version 2 or later at the following locations:
		*
		* http://www.opensource.org/licenses/gpl-license.html
		* http://www.gnu.org/copyleft/gpl.html
		*/

		#include <linux/init.h>
		#include <linux/io.h>
		#include <linux/module.h>
		#include <linux/of.h>
		#include <linux/of_address.h>
		#include <linux/of_device.h>

		#define MMDC_MAPSR 0x404
		#define BP_MMDC_MAPSR_PSD 0
		#define BP_MMDC_MAPSR_PSS 4

		static int __devinit imx_mmdc_probe(struct platform_device *pdev)
		{
		struct device_node *np = pdev->dev.of_node;
		void __iomem mmdc_base, reg;
		u32 val;
		int timeout = 0x400;

		mmdc_base = of_iomap(np, 0);
		WARN_ON(!mmdc_base);

		reg = mmdc_base + MMDC_MAPSR;

		/* Enable automatic power saving */
		val = readl_relaxed(reg);
		val &= ~(1 << BP_MMDC_MAPSR_PSD);
		writel_relaxed(val, reg);

		/* Ensure it's successfully enabled */
		while (!(readl_relaxed(reg) & 1 << BP_MMDC_MAPSR_PSS) && --timeout)
		cpu_relax();

		if (unlikely(!timeout)) {
		pr_warn("%s: failed to enable automatic power saving\n",
		__func__);
		return -EBUSY;
		}

		return 0;
		}

		static struct of_device_id imx_mmdc_dt_ids[] = {
		{ .compatible = "fsl,imx6q-mmdc", },
		{ /* sentinel */ }
		};

		static struct platform_driver imx_mmdc_driver = {
		.driver = {
		.name = "imx-mmdc",
		.owner = THIS_MODULE,
		.of_match_table = imx_mmdc_dt_ids,
		},
		.probe = imx_mmdc_probe,
		};

		static int __init imx_mmdc_init(void)
		{
		return platform_driver_register(&imx_mmdc_driver);
		}
		postcore_initcall(imx_mmdc_init);