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Commit 9f405100 authored by Chris Wilson's avatar Chris Wilson Committed by Keith Packard
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drm/i915: Replace ironlake_compute_wm0 with g4x_compute_wm0 



The computation of the first-level watermarks for g4x and gen5+ are
based on the same algorithm, so we can refactor those code paths to
use a single function.

Note that g4x_compute_wm0 takes a 'plane' argument while
ironlake_compute_wm0 took a 'pipe' argument. Both should have used a
'plane' argument, so this patch fixes that as well (not that it caused
a problem; ironlake always uses pipe == plane).

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarKeith Packard <keithp@keithp.com>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent bf3301ab

drivers/gpu/drm/i915/intel_display.c

+20 −68
Original line number Diff line number Diff line
@@ -3983,54 +3983,6 @@ static void i830_update_wm(struct drm_device *dev) 
#define ILK_LP0_PLANE_LATENCY		700

#define ILK_LP0_CURSOR_LATENCY		1300



static bool ironlake_compute_wm0(struct drm_device *dev,

				 int pipe,

				 const struct intel_watermark_params *display,

				 int display_latency_ns,

				 const struct intel_watermark_params *cursor,

				 int cursor_latency_ns,

				 int *plane_wm,

				 int *cursor_wm)

{

	struct drm_crtc *crtc;

	int htotal, hdisplay, clock, pixel_size;

	int line_time_us, line_count;

	int entries, tlb_miss;



	crtc = intel_get_crtc_for_pipe(dev, pipe);

	if (crtc->fb == NULL || !crtc->enabled)

		return false;



	htotal = crtc->mode.htotal;

	hdisplay = crtc->mode.hdisplay;

	clock = crtc->mode.clock;

	pixel_size = crtc->fb->bits_per_pixel / 8;



	/* Use the small buffer method to calculate plane watermark */

	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;

	tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;

	if (tlb_miss > 0)

		entries += tlb_miss;

	entries = DIV_ROUND_UP(entries, display->cacheline_size);

	*plane_wm = entries + display->guard_size;

	if (*plane_wm > (int)display->max_wm)

		*plane_wm = display->max_wm;



	/* Use the large buffer method to calculate cursor watermark */

	line_time_us = ((htotal * 1000) / clock);

	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;

	entries = line_count * 64 * pixel_size;

	tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;

	if (tlb_miss > 0)

		entries += tlb_miss;

	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);

	*cursor_wm = entries + cursor->guard_size;

	if (*cursor_wm > (int)cursor->max_wm)

		*cursor_wm = (int)cursor->max_wm;



	return true;

}



/*

 * Check the wm result.

 *
@@ -4139,7 +4091,7 @@ static void ironlake_update_wm(struct drm_device *dev) 
	unsigned int enabled;



	enabled = 0;

	if (ironlake_compute_wm0(dev, 0,

	if (g4x_compute_wm0(dev, 0,

			    &ironlake_display_wm_info,

			    ILK_LP0_PLANE_LATENCY,

			    &ironlake_cursor_wm_info,
@@ -4153,7 +4105,7 @@ static void ironlake_update_wm(struct drm_device *dev) 
		enabled |= 1;

	}



	if (ironlake_compute_wm0(dev, 1,

	if (g4x_compute_wm0(dev, 1,

			    &ironlake_display_wm_info,

			    ILK_LP0_PLANE_LATENCY,

			    &ironlake_cursor_wm_info,
@@ -4223,7 +4175,7 @@ static void sandybridge_update_wm(struct drm_device *dev) 
	unsigned int enabled;



	enabled = 0;

	if (ironlake_compute_wm0(dev, 0,

	if (g4x_compute_wm0(dev, 0,

			    &sandybridge_display_wm_info, latency,

			    &sandybridge_cursor_wm_info, latency,

			    &plane_wm, &cursor_wm)) {
@@ -4235,7 +4187,7 @@ static void sandybridge_update_wm(struct drm_device *dev) 
		enabled |= 1;

	}



	if (ironlake_compute_wm0(dev, 1,

	if (g4x_compute_wm0(dev, 1,

			    &sandybridge_display_wm_info, latency,

			    &sandybridge_cursor_wm_info, latency,

			    &plane_wm, &cursor_wm)) {