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Commit 9f2edd41 authored by Shinya Kuribayashi's avatar Shinya Kuribayashi Committed by Laurent Pinchart
Browse files

sh-pfc: r8a7790: Remove deprecated Ethernet MII/RMII pins 



The pins have been removed from the datasheet, remove them here as well.

Signed-off-by: default avatarShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
parent bcec7475

drivers/pinctrl/sh-pfc/pfc-r8a7790.c

+94 −130
Original line number Original line Diff line number Diff line
@@ -171,15 +171,15 @@ enum { 
	FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,

	FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,

	FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,

	FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,

	FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,

	FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,

	FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,

	FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,

	FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,

	FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,





	/* IPSR1 */

	/* IPSR1 */

	FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,

	FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,

	FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,

	FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,

	FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,

	FN_SCIFA1_TXD_C, FN_AVB_TXD2,

	FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,

	FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,

	FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,

	FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,

	FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,

	FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,

	FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,

	FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,

	FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,

	FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
@@ -266,29 +266,29 @@ enum { 
	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,

	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,

	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,

	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,

	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,

	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,

	FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,

	FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,

	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,

	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,

	FN_I2C2_SCL_E, FN_ETH_RX_ER, FN_RMII_RX_ER,

	FN_I2C2_SCL_E, FN_ETH_RX_ER,

	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,

	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,

	FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, FN_RMII_RXD0,

	FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,

	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,

	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,

	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,

	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,

	FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,

	FN_HRX0_E, FN_STP_ISSYNC_0_B,

	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,

	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,

	FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,

	FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,

	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,

	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,

	FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,

	FN_ETH_REF_CLK, FN_HCTS0_N_E,

	FN_STP_IVCXO27_1_B, FN_HRX0_F,

	FN_STP_IVCXO27_1_B, FN_HRX0_F,





	/* IPSR7 */

	/* IPSR7 */

	FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,

	FN_ETH_MDIO, FN_HRTS0_N_E,

	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,

	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,

	FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,

	FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,

	FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,

	FN_ETH_TX_EN, FN_SIM0_CLK_C,

	FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,

	FN_HRTS0_N_F, FN_ETH_MAGIC,

	FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,

	FN_SIM0_RST_C, FN_ETH_TXD0,

	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,

	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,

	FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,

	FN_ETH_MDC, FN_STP_ISD_1_B,

	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,

	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,

	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,

	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,

	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,

	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
@@ -296,26 +296,25 @@ enum { 
	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,

	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,

	FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,

	FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,

	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,

	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,

	FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,

	FN_ATACS00_N, FN_AVB_RXD1,

	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,

	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,

	FN_MII_RXD2,





	/* IPSR8 */

	/* IPSR8 */

	FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,

	FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,

	FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,

	FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,

	FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,

	FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,

	FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,

	FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,

	FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,

	FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,

	FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,

	FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,

	FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,

	FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,

	FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,

	FN_VI1_CLK, FN_AVB_RX_DV,

	FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,

	FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,

	FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,

	FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,

	FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,

	FN_SCIFA1_RXD_D, FN_AVB_MDC,

	FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,

	FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,

	FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,

	FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,

	FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,

	FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,

	FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,

	FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,

	FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,

	FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,

	FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,

	FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,

	FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,

	FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
@@ -331,13 +330,13 @@ enum { 
	FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,

	FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,

	FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,

	FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,

	FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,

	FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,

	FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,

	FN_AVB_TX_EN, FN_SD1_CMD,

	FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,

	FN_AVB_TX_ER, FN_SCIFB0_SCK_B,

	FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,

	FN_SD1_DAT0, FN_AVB_TX_CLK,

	FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,

	FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,

	FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,

	FN_SCIFB0_TXD_B, FN_SD1_DAT2,

	FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,

	FN_AVB_COL, FN_SCIFB0_CTS_N_B,

	FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,

	FN_SD1_DAT3, FN_AVB_RXD0,

	FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,

	FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,

	FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,

	FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,

	FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,

	FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
@@ -551,14 +550,14 @@ enum { 
	IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,

	IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,

	I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,

	I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,

	VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK,

	VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK,

	D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,

	D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,

	VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,

	VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,





	D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,

	D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,

	VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,

	VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,

	SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,

	SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,

	VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,

	VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,

	SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,

	SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,

	VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,

	VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,

	D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,

	D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,

	VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,

	VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
@@ -641,28 +640,28 @@ enum { 
	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,

	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,

	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,

	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,

	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,

	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,

	ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,

	ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,

	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,

	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,

	I2C2_SCL_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,

	I2C2_SCL_E_MARK, ETH_RX_ER_MARK,

	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,

	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,

	IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,

	IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,

	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,

	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,

	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,

	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,

	RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,

	HRX0_E_MARK, STP_ISSYNC_0_B_MARK,

	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,

	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,

	RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,

	RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,

	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,

	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,

	ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,

	ETH_REF_CLK_MARK, HCTS0_N_E_MARK,

	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,

	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,





	ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,

	ETH_MDIO_MARK, HRTS0_N_E_MARK,

	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,

	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,

	RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,

	HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,

	ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,

	ETH_TX_EN_MARK, SIM0_CLK_C_MARK,

	HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,

	HRTS0_N_F_MARK, ETH_MAGIC_MARK,

	SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,

	SIM0_RST_C_MARK, ETH_TXD0_MARK,

	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,

	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,

	ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,

	ETH_MDC_MARK, STP_ISD_1_B_MARK,

	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,

	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,

	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,

	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,

	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,

	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
@@ -670,25 +669,24 @@ enum { 
	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,

	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,

	PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,

	PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,

	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,

	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,

	ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,

	ATACS00_N_MARK, AVB_RXD1_MARK,

	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,

	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,

	MII_RXD2_MARK,





	VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,

	VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,

	MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,

	VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,

	AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,

	AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,

	AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,

	AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,

	AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,

	AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,

	AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,

	AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,

	MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,

	VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,

	MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,

	VI1_CLK_MARK, AVB_RX_DV_MARK,

	MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,

	VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,

	AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,

	AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,

	SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,

	SCIFA1_RXD_D_MARK, AVB_MDC_MARK,

	VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,

	VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,

	MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,

	VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,

	AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,

	AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,

	AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,

	AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,

	AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,

	AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,

	SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,

	SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,

	SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,

	SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
@@ -703,13 +701,13 @@ enum { 
	MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,

	MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,

	GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,

	GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,

	I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,

	I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,

	AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,

	AVB_TX_EN_MARK, SD1_CMD_MARK,

	AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,

	AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,

	SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,

	SD1_DAT0_MARK, AVB_TX_CLK_MARK,

	SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,

	SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,

	MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,

	SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,

	AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,

	AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,

	SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,

	SD1_DAT3_MARK, AVB_RXD0_MARK,

	SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,

	SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,

	TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,

	TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,

	IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,

	IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
@@ -907,7 +905,6 @@ static const pinmux_enum_t pinmux_data[] = { 
	PINMUX_IPSR_DATA(IP0_30_27, D8),

	PINMUX_IPSR_DATA(IP0_30_27, D8),

	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),

	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),

	PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),

	PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),

	PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0),

	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),

	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),

	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),

	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
@@ -915,21 +912,18 @@ static const pinmux_enum_t pinmux_data[] = { 
	PINMUX_IPSR_DATA(IP1_3_0, D9),

	PINMUX_IPSR_DATA(IP1_3_0, D9),

	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),

	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),

	PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),

	PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),

	PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1),

	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),

	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),

	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),

	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),

	PINMUX_IPSR_DATA(IP1_7_4, D10),

	PINMUX_IPSR_DATA(IP1_7_4, D10),

	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),

	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),

	PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),

	PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),

	PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2),

	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),

	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),

	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),

	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),

	PINMUX_IPSR_DATA(IP1_11_8, D11),

	PINMUX_IPSR_DATA(IP1_11_8, D11),

	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),

	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),

	PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),

	PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),

	PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3),

	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),

	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),

	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),

	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
@@ -1205,28 +1199,24 @@ static const pinmux_enum_t pinmux_data[] = { 
	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),

	PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),

	PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),

	PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),

	PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),

	PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),

	PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),

	PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),

	PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),

	PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),

	PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),

	PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),

	PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),

	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),

	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
@@ -1234,41 +1224,33 @@ static const pinmux_enum_t pinmux_data[] = { 
	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),

	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),

	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),

	PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),

	PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),

	PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),

	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),

	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),

	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),

	PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),

	PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),

	PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),

	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),

	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),





	PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),

	PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),

	PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),

	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),

	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),

	PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),

	PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),

	PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),

	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),

	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),

	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),

	PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),

	PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),

	PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),

	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),

	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),

	PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),

	PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),

	PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),

	PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),

	PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),

	PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),

	PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),

	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),

	PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),

	PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),

	PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),

	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),

	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),

	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
@@ -1294,16 +1276,13 @@ static const pinmux_enum_t pinmux_data[] = { 
	PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),

	PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),

	PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),

	PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),

	PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),

	PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),

	PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),

	PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),

	PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),

	PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),

	PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),

	PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),





	PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),

	PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),

	PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),

	PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),

	PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),

	PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),

	PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),

	PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),

	PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),

	PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),

	PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
@@ -1318,32 +1297,25 @@ static const pinmux_enum_t pinmux_data[] = { 
	PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),

	PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),

	PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),

	PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),

	PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),

	PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),

	PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),

	PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),

	PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),

	PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),

	PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),

	PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),

	PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),

	PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),

	PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),

	PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),

	PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),

	PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),

	PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),

	PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),

	PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),

	PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),

	PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),

	PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),

	PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),

	PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),

	PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),

	PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),

	PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),

	PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),

	PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),

	PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),

	PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),

	PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),

	PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),

	PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),

	PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),

	PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),

	PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),

	PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),

	PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),

	PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
@@ -1386,26 +1358,20 @@ static const pinmux_enum_t pinmux_data[] = { 
	PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),

	PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),

	PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),

	PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),

	PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),

	PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),

	PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),

	PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),

	PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),

	PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),

	PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),

	PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),

	PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),

	PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),

	PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),

	PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),

	PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),

	PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),

	PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),

	PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),

	PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),

	PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),

	PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),

	PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),

	PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),

	PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),

	PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),

	PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),

	PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),

	PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),

	PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),

	PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),

	PINMUX_IPSR_DATA(IP9_25_24, MII_COL),

	PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),

	PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),

	PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),

	PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),

	PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),

	PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),

	PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),

	PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),

	PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),

	PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),

	PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),

	PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),

	PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
@@ -3257,7 +3223,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP0_31 [1] */

		/* IP0_31 [1] */

		0, 0,

		0, 0,

		/* IP0_30_27 [4] */

		/* IP0_30_27 [4] */

		FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,

		FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,

		FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,

		FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,

		0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP0_26_23 [4] */

		/* IP0_26_23 [4] */
@@ -3313,15 +3279,15 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,

		FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,

		0, 0,

		0, 0,

		/* IP1_11_8 [4] */

		/* IP1_11_8 [4] */

		FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,

		FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,

		FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,

		FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,

		0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP1_7_4 [4] */

		/* IP1_7_4 [4] */

		FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,

		FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,

		FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,

		FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,

		0, 0, 0, 0, 0, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0,

		/* IP1_3_0 [4] */

		/* IP1_3_0 [4] */

		FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,

		FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,

		FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,

		FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,

		0, 0, 0, 0, 0, 0, 0, 0, 0, }

		0, 0, 0, 0, 0, 0, 0, 0, 0, }

	},

	},
@@ -3461,22 +3427,22 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 
	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,

	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,

			     3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {

			     3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {

		/* IP6_31_29 [3] */

		/* IP6_31_29 [3] */

		FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,

		FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,

		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,

		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,

		/* IP6_28_26 [3] */

		/* IP6_28_26 [3] */

		FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,

		FN_ETH_LINK, 0, FN_HTX0_E,

		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,

		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,

		/* IP6_25_23 [3] */

		/* IP6_25_23 [3] */

		FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,

		FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,

		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,

		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,

		/* IP6_22_20 [3] */

		/* IP6_22_20 [3] */

		FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,

		FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,

		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,

		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,

		/* IP6_19_17 [3] */

		/* IP6_19_17 [3] */

		FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,

		FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,

		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,

		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,

		/* IP6_16_14 [3] */

		/* IP6_16_14 [3] */

		FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,

		FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,

		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,

		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,

		FN_I2C2_SCL_E, 0,

		FN_I2C2_SCL_E, 0,

		/* IP6_13_11 [3] */

		/* IP6_13_11 [3] */
@@ -3499,10 +3465,9 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP7_31 [1] */

		/* IP7_31 [1] */

		0, 0,

		0, 0,

		/* IP7_30_29 [2] */

		/* IP7_30_29 [2] */

		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,

		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,

		FN_MII_RXD2,

		/* IP7_28_27 [2] */

		/* IP7_28_27 [2] */

		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,

		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,

		/* IP7_26_25 [2] */

		/* IP7_26_25 [2] */

		FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,

		FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,

		/* IP7_24_22 [3] */

		/* IP7_24_22 [3] */
@@ -3515,20 +3480,20 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,

		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,

		FN_GLO_SS_C, 0, 0, 0,

		FN_GLO_SS_C, 0, 0, 0,

		/* IP7_15_13 [3] */

		/* IP7_15_13 [3] */

		FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,

		FN_ETH_MDC, 0, FN_STP_ISD_1_B,

		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,

		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,

		/* IP7_12_10 [3] */

		/* IP7_12_10 [3] */

		FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,

		FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,

		FN_GLO_SCLK_C, 0, 0, 0,

		FN_GLO_SCLK_C, 0, 0, 0,

		/* IP7_9_8 [2] */

		/* IP7_9_8 [2] */

		FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,

		FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,

		/* IP7_7_6 [2] */

		/* IP7_7_6 [2] */

		FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,

		FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,

		/* IP7_5_3 [3] */

		/* IP7_5_3 [3] */

		FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,

		FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,

		0, 0, 0,

		0, 0, 0,

		/* IP7_2_0 [3] */

		/* IP7_2_0 [3] */

		FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,

		FN_ETH_MDIO, 0, FN_HRTS0_N_E,

		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }

		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }

	},

	},

	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,

	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
@@ -3546,22 +3511,21 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,

		FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,

		/* IP8_25_24 [2] */

		/* IP8_25_24 [2] */

		FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,

		FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,

		FN_AVB_MAGIC, FN_MII_MAGIC,

		FN_AVB_MAGIC, 0,

		/* IP8_23_22 [2] */

		/* IP8_23_22 [2] */

		FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,

		FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,

		/* IP8_21_20 [2] */

		/* IP8_21_20 [2] */

		FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,

		FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,

		FN_MII_MDIO,

		/* IP8_19_18 [2] */

		/* IP8_19_18 [2] */

		FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,

		FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,

		/* IP8_17_16 [2] */

		/* IP8_17_16 [2] */

		FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,

		FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,

		/* IP8_15_14 [2] */

		/* IP8_15_14 [2] */

		FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,

		FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,

		/* IP8_13_12 [2] */

		/* IP8_13_12 [2] */

		FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,

		FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,

		/* IP8_11_10 [2] */

		/* IP8_11_10 [2] */

		FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,

		FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,

		/* IP8_9_8 [2] */

		/* IP8_9_8 [2] */

		FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,

		FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,

		/* IP8_7_6 [2] */

		/* IP8_7_6 [2] */
@@ -3571,7 +3535,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP8_3_2 [2] */

		/* IP8_3_2 [2] */

		FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,

		FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,

		/* IP8_1_0 [2] */

		/* IP8_1_0 [2] */

		FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }

		FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }

	},

	},

	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,

	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,

			     4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {

			     4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
@@ -3580,17 +3544,17 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,

		FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,

		FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,

		FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,

		/* IP9_27_26 [2] */

		/* IP9_27_26 [2] */

		FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,

		FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,

		/* IP9_25_24 [2] */

		/* IP9_25_24 [2] */

		FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,

		FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,

		/* IP9_23_22 [2] */

		/* IP9_23_22 [2] */

		FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,

		FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,

		/* IP9_21_20 [2] */

		/* IP9_21_20 [2] */

		FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,

		FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,

		/* IP9_19_18 [2] */

		/* IP9_19_18 [2] */

		FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,

		FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,

		/* IP9_17_16 [2] */

		/* IP9_17_16 [2] */

		FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,

		FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,

		/* IP9_15_12 [4] */

		/* IP9_15_12 [4] */

		FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,

		FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,

		FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,

		FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,