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Commit 9f0096a1 authored by Dmitry Kravkov's avatar Dmitry Kravkov Committed by David S. Miller
Browse files

bnx2x: properly clean indirect addresses 



Signed-off-by: default avatarDmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2031bd3a

drivers/net/bnx2x/bnx2x_main.c

+11 −4
Original line number Diff line number Diff line
@@ -10259,10 +10259,17 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev, 
	/* clean indirect addresses */

	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,

			       PCICFG_VENDOR_ID_OFFSET);

	REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);

	/* Clean the following indirect addresses for all functions since it

	 * is not used by the driver.

	 */

	REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);

	REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);



	/*

	 * Enable internal target-read (in case we are probed after PF FLR).

drivers/net/bnx2x/bnx2x_reg.h

+21 −5
Original line number Diff line number Diff line
@@ -3009,9 +3009,25 @@ 
/* [R 7] Debug only: Number of used entries in the header FIFO */

#define PXP2_REG_HST_HEADER_FIFO_STATUS				 0x120478

#define PXP2_REG_PGL_ADDR_88_F0					 0x120534

/* [R 32] GRC address for configuration access to PCIE config address 0x88.

 * any write to this PCIE address will cause a GRC write access to the

 * address that's in t this register */

#define PXP2_REG_PGL_ADDR_88_F1					 0x120544

#define PXP2_REG_PGL_ADDR_8C_F0					 0x120538

/* [R 32] GRC address for configuration access to PCIE config address 0x8c.

 * any write to this PCIE address will cause a GRC write access to the

 * address that's in t this register */

#define PXP2_REG_PGL_ADDR_8C_F1					 0x120548

#define PXP2_REG_PGL_ADDR_90_F0					 0x12053c

/* [R 32] GRC address for configuration access to PCIE config address 0x90.

 * any write to this PCIE address will cause a GRC write access to the

 * address that's in t this register */

#define PXP2_REG_PGL_ADDR_90_F1					 0x12054c

#define PXP2_REG_PGL_ADDR_94_F0					 0x120540

/* [R 32] GRC address for configuration access to PCIE config address 0x94.

 * any write to this PCIE address will cause a GRC write access to the

 * address that's in t this register */

#define PXP2_REG_PGL_ADDR_94_F1					 0x120550

#define PXP2_REG_PGL_CONTROL0					 0x120490

#define PXP2_REG_PGL_CONTROL1					 0x120514

#define PXP2_REG_PGL_DEBUG					 0x120520