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Commit 9dd4ffdf authored by Chon Ming Lee's avatar Chon Ming Lee Committed by Daniel Vetter
Browse files

drm/i915: Modify DP set clock to accomodate more eDP timings v2 



eDP 1.4 supports 4-5 extra link rates in additional to current 2 link
rate.  Create a structure to store the DPLL divisor data to improve
readability.

v2: Fix the gen4_dpll/pch_dpll initialization to C99
designated initializers, and use a single loop for all platforms. (Jani and Daniel)

Signed-off-by: default avatarChon Ming Lee <chon.ming.lee@intel.com>
[danvet: Fix up checkpatch warnings.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8807e55b

drivers/gpu/drm/i915/intel_dp.c

+35 −28
Original line number Original line Diff line number Diff line
@@ -38,6 +38,25 @@ 




#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)





struct dp_link_dpll {

	int link_bw;

	struct dpll dpll;

};



static const struct dp_link_dpll gen4_dpll[] = {

	{ DP_LINK_BW_1_62,

		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },

	{ DP_LINK_BW_2_7,

		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }

};



static const struct dp_link_dpll pch_dpll[] = {

	{ DP_LINK_BW_1_62,

		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },

	{ DP_LINK_BW_2_7,

		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }

};



/**

/**

 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)

 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)

 * @intel_dp: DP struct

 * @intel_dp: DP struct
@@ -649,42 +668,30 @@ intel_dp_set_clock(struct intel_encoder *encoder, 
		   struct intel_crtc_config *pipe_config, int link_bw)

		   struct intel_crtc_config *pipe_config, int link_bw)

{

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_device *dev = encoder->base.dev;

	const struct dp_link_dpll *divisor = NULL;

	int i, count = 0;





	if (IS_G4X(dev)) {

	if (IS_G4X(dev)) {

		if (link_bw == DP_LINK_BW_1_62) {

		divisor = gen4_dpll;

			pipe_config->dpll.p1 = 2;

		count = ARRAY_SIZE(gen4_dpll);

			pipe_config->dpll.p2 = 10;

			pipe_config->dpll.n = 2;

			pipe_config->dpll.m1 = 23;

			pipe_config->dpll.m2 = 8;

		} else {

			pipe_config->dpll.p1 = 1;

			pipe_config->dpll.p2 = 10;

			pipe_config->dpll.n = 1;

			pipe_config->dpll.m1 = 14;

			pipe_config->dpll.m2 = 2;

		}

		pipe_config->clock_set = true;

	} else if (IS_HASWELL(dev)) {

	} else if (IS_HASWELL(dev)) {

		/* Haswell has special-purpose DP DDI clocks. */

		/* Haswell has special-purpose DP DDI clocks. */

	} else if (HAS_PCH_SPLIT(dev)) {

	} else if (HAS_PCH_SPLIT(dev)) {

		if (link_bw == DP_LINK_BW_1_62) {

		divisor = pch_dpll;

			pipe_config->dpll.n = 1;

		count = ARRAY_SIZE(pch_dpll);

			pipe_config->dpll.p1 = 2;

			pipe_config->dpll.p2 = 10;

			pipe_config->dpll.m1 = 12;

			pipe_config->dpll.m2 = 9;

		} else {

			pipe_config->dpll.n = 2;

			pipe_config->dpll.p1 = 1;

			pipe_config->dpll.p2 = 10;

			pipe_config->dpll.m1 = 14;

			pipe_config->dpll.m2 = 8;

		}

		pipe_config->clock_set = true;

	} else if (IS_VALLEYVIEW(dev)) {

	} else if (IS_VALLEYVIEW(dev)) {

		/* FIXME: Need to figure out optimized DP clocks for vlv. */

		/* FIXME: Need to figure out optimized DP clocks for vlv. */

	}

	}



	if (divisor && count) {

		for (i = 0; i < count; i++) {

			if (link_bw == divisor[i].link_bw) {

				pipe_config->dpll = divisor[i].dpll;

				pipe_config->clock_set = true;

				break;

			}

		}

	}

}

}





bool

bool