Merge "ARM: dts: msm: Configure SPI_2, SPI_4 and UART2 instance for MSM8909" (9d67f9b1) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/boot/dts/qcom/msm8909-pinctrl.dtsi

+181 −1

Original line number	Diff line number	Diff line
		/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -43,6 +43,84 @@
		};
		};

		blsp1_uart2_tx_active: blsp1_uart2_tx_active {
		mux {
		pins = "gpio20";
		function = "blsp_uart2_a";
		};

		config {
		pins = "gpio20";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart2_tx_sleep: blsp1_uart2_tx_sleep {
		mux {
		pins = "gpio20";
		function = "gpio";
		};

		config {
		pins = "gpio20";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		blsp1_uart2_rxcts_active: blsp1_uart2_rxcts_active {
		mux {
		pins = "gpio21", "gpio111";
		function = "blsp_uart2_a";
		};

		config {
		pins = "gpio21", "gpio111";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart2_rxcts_sleep: blsp1_uart2_rxcts_sleep {
		mux {
		pins = "gpio21", "gpio111";
		function = "gpio";
		};

		config {
		pins = "gpio21", "gpio111";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		blsp1_uart2_rfr_active: blsp1_uart2_rfr_active {
		mux {
		pins = "gpio112";
		function = "blsp_uart2_a";
		};

		config {
		pins = "gpio112";
		drive-strength = <2>;
		bias-disable;
		};
		};

		blsp1_uart2_rfr_sleep: blsp1_uart2_rfr_sleep {
		mux {
		pins = "gpio112";
		function = "gpio";
		};

		config {
		pins = "gpio112";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		pmx_mdss {
		mdss_dsi_active: mdss_dsi_active {
		mux {
		@@ -148,6 +226,108 @@
		};
		};

		spi2 {
		spi2_default: spi2_default {
		mux {
		pins = "gpio20", "gpio21",
		"gpio112";
		function = "blsp_spi2";
		};
		config {
		pins = "gpio20", "gpio21",
		"gpio112";
		drive-strength = <12>; /* 12 MA */
		bias-disable; /* No PULL */
		};
		};
		spi2_sleep: spi2_sleep {
		mux {
		pins = "gpio20", "gpio21",
		"gpio112";
		function = "gpio";
		};
		config {
		pins = "gpio20", "gpio21",
		"gpio112";
		drive-strength = <2>; /* 2 MA */
		bias-pull-down; /* pull down */
		};
		};
		spi2_cs0_active: spi2_cs0_active {
		mux {
		pins = "gpio111";
		function = "blsp_spi2";
		};
		config {
		pins = "gpio111";
		drive-strength = <2>;
		bias-disable;
		};
		};
		spi2_cs0_sleep: spi2_cs0_sleep {
		mux {
		pins = "gpio111";
		function = "gpio";
		};
		config {
		pins = "gpio111";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		spi4 {
		spi4_default: spi4_default {
		mux {
		pins = "gpio12", "gpio13",
		"gpio15";
		function = "blsp_spi4";
		};
		config {
		pins = "gpio12", "gpio13",
		"gpio15";
		drive-strength = <12>; /* 12 MA */
		bias-disable; /* No PULL */
		};
		};
		spi4_sleep: spi4_sleep {
		mux {
		pins = "gpio12", "gpio13",
		"gpio15";
		function = "gpio";
		};
		config {
		pins = "gpio12", "gpio13",
		"gpio15";
		drive-strength = <2>; /* 2 MA */
		bias-pull-down; /* pull down */
		};
		};
		spi4_cs0_active: spi4_cs0_active {
		mux {
		pins = "gpio14";
		function = "blsp_spi4";
		};
		config {
		pins = "gpio14";
		drive-strength = <2>;
		bias-disable;
		};
		};
		spi4_cs0_sleep: spi4_cs0_sleep {
		mux {
		pins = "gpio14";
		function = "gpio";
		};
		config {
		pins = "gpio14";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		pmx_i2c_1 {
		i2c_1_active: i2c_1_active {
		mux {

arch/arm/boot/dts/qcom/msm8909.dtsi

+93 −2

Original line number	Diff line number	Diff line
		@@ -43,6 +43,8 @@
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
		spi0 = &spi_0; /* SPI0 controller device */
		spi2 = &spi_2;
		spi4 = &spi_4;
		i2c5 = &i2c_5; /* I2c5 cntroller device */
		i2c3 = &i2c_3; /* I2C3 controller */
		i2c1 = &i2c_1; /* I2C1 controller */
		@@ -391,6 +393,43 @@
		clock-names = "core_clk", "iface_clk";
		};

		blsp1_uart2_hs: uart@78b0000 { /BLSP1 UART2/
		compatible = "qcom,msm-hsuart-v14";
		reg = <0x78b0000 0x200>,
		<0x7884000 0x1f000>;
		reg-names = "core_mem", "bam_mem";
		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
		#address-cells = <0>;
		interrupt-parent = <&blsp1_uart2_hs>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 108 0
		1 &intc 0 238 0
		2 &msm_gpio 21 0>;
		qcom,inject-rx-on-wakeup;
		qcom,rx-char-to-inject = <0xfd>;
		qcom,master-id = <86>;
		clock-names = "core_clk", "iface_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
		<&clock_gcc clk_gcc_blsp1_ahb_clk>;
		pinctrl-names = "sleep", "default";
		pinctrl-0 = <&blsp1_uart2_tx_sleep>, <&blsp1_uart2_rxcts_sleep>,
		<&blsp1_uart2_rfr_sleep>;
		pinctrl-1 = <&blsp1_uart2_tx_active>,
		<&blsp1_uart2_rxcts_active>, <&blsp1_uart2_rfr_active>;

		qcom,bam-tx-ep-pipe-index = <2>;
		qcom,bam-rx-ep-pipe-index = <3>;
		qcom,msm-bus,name = "blsp1_uart2_hs";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
		<86 512 0 0>,
		<86 512 500 800>;
		status = "disabled";
		};

		qcom,sps {
		compatible = "qcom,msm_sps_4k";
		qcom,device-type = <3>;
		@@ -1123,6 +1162,58 @@
		qcom,master-id = <86>;
		};

		spi_2: spi@78b6000 { /* BLSP1 QUP2 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x78b6000 0x600>,
		<0x7884000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 96 0>, <0 238 0>;
		spi-max-frequency = <50000000>;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi2_default &spi2_cs0_active>;
		pinctrl-1 = <&spi2_sleep &spi2_cs0_sleep>;
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
		<&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>;
		clock-names = "iface_clk", "core_clk";
		qcom,infinite-mode = <0>;
		qcom,use-bam;
		qcom,use-pinctrl;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <6>;
		qcom,bam-producer-pipe-index = <7>;
		qcom,master-id = <86>;
		status = "disabled";
		};

		spi_4: spi@78B8000{ /* BLSP1 QUP4 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x78b8000 0x600>,
		<0x7884000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 98 0>, <0 238 0>;
		spi-max-frequency = <50000000>;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi4_default &spi4_cs0_active>;
		pinctrl-1 = <&spi4_sleep &spi4_cs0_sleep>;
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
		<&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>;
		clock-names = "iface_clk", "core_clk";
		qcom,infinite-mode = <0>;
		qcom,use-bam;
		qcom,use-pinctrl;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <10>;
		qcom,bam-producer-pipe-index = <11>;
		qcom,master-id = <86>;
		status = "disabled";
		};

		dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */
		#dma-cells = <4>;
		compatible = "qcom,sps-dma";