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Commit 9d56851e authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge remote-tracking branch 'scott/next' into next 

Latest FSL updates from Scott:

<<
Highlights include changes in compiler flag settings
on e500 family cores, booke64 hibernation support, support for two new
boards, and an erratum workaround.
>>
parents afbcdd97 622e03eb

Documentation/devicetree/bindings/crypto/fsl-sec6.txt

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SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).

Currently Freescale powerpc chip C29X is embeded with SEC 6.

SEC 6 device tree binding include:

   -SEC 6 Node

   -Job Ring Node

   -Full Example



=====================================================================

SEC 6 Node



Description



    Node defines the base address of the SEC 6 block.

    This block specifies the address range of all global

    configuration registers for the SEC 6 block.

    For example, In C293, we could see three SEC 6 node.



PROPERTIES



   - compatible

      Usage: required

      Value type: <string>

      Definition: Must include "fsl,sec-v6.0".



   - fsl,sec-era

      Usage: optional

      Value type: <u32>

      Definition: A standard property. Define the 'ERA' of the SEC

          device.



   - #address-cells

       Usage: required

       Value type: <u32>

       Definition: A standard property.  Defines the number of cells

           for representing physical addresses in child nodes.



   - #size-cells

       Usage: required

       Value type: <u32>

       Definition: A standard property.  Defines the number of cells

           for representing the size of physical addresses in

           child nodes.



   - reg

      Usage: required

      Value type: <prop-encoded-array>

      Definition: A standard property.  Specifies the physical

          address and length of the SEC 6 configuration registers.



   - ranges

       Usage: required

       Value type: <prop-encoded-array>

       Definition: A standard property.  Specifies the physical address

           range of the SEC 6.0 register space (-SNVS not included).  A

           triplet that includes the child address, parent address, &

           length.



   Note: All other standard properties (see the ePAPR) are allowed

   but are optional.



EXAMPLE

	crypto@a0000 {

		compatible = "fsl,sec-v6.0";

		fsl,sec-era = <6>;

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0xa0000 0x20000>;

		ranges = <0 0xa0000 0x20000>;

	};



=====================================================================

Job Ring (JR) Node



    Child of the crypto node defines data processing interface to SEC 6

    across the peripheral bus for purposes of processing

    cryptographic descriptors. The specified address

    range can be made visible to one (or more) cores.

    The interrupt defined for this node is controlled within

    the address range of this node.



  - compatible

      Usage: required

      Value type: <string>

      Definition: Must include "fsl,sec-v6.0-job-ring".



  - reg

      Usage: required

      Value type: <prop-encoded-array>

      Definition: Specifies a two JR parameters:  an offset from

           the parent physical address and the length the JR registers.



   - interrupts

      Usage: required

      Value type: <prop_encoded-array>

      Definition:  Specifies the interrupts generated by this

           device.  The value of the interrupts property

           consists of one interrupt specifier. The format

           of the specifier is defined by the binding document

           describing the node's interrupt parent.



EXAMPLE

	jr@1000 {

		compatible = "fsl,sec-v6.0-job-ring";

		reg = <0x1000 0x1000>;

		interrupts = <49 2 0 0>;

	};



===================================================================

Full Example



Since some chips may contain more than one SEC, the dtsi contains

only the node contents, not the node itself.  A chip using the SEC

should include the dtsi inside each SEC node.  Example:



In qoriq-sec6.0.dtsi:



	compatible = "fsl,sec-v6.0";

	fsl,sec-era = <6>;

	#address-cells = <1>;

	#size-cells = <1>;



	jr@1000 {

		compatible = "fsl,sec-v6.0-job-ring",

			     "fsl,sec-v5.2-job-ring",

			     "fsl,sec-v5.0-job-ring",

			     "fsl,sec-v4.4-job-ring",

			     "fsl,sec-v4.0-job-ring";

		reg	   = <0x1000 0x1000>;

	};



	jr@2000 {

		compatible = "fsl,sec-v6.0-job-ring",

			     "fsl,sec-v5.2-job-ring",

			     "fsl,sec-v5.0-job-ring",

			     "fsl,sec-v4.4-job-ring",

			     "fsl,sec-v4.0-job-ring";

		reg	   = <0x2000 0x1000>;

	};



In the C293 device tree, we add the include of public property:



	crypto@a0000 {

		/include/ "qoriq-sec6.0.dtsi"

	}



	crypto@a0000 {

		reg = <0xa0000 0x20000>;

		ranges = <0 0xa0000 0x20000>;



		jr@1000 {

			interrupts = <49 2 0 0>;

		};



		jr@2000 {

			interrupts = <50 2 0 0>;

		};

	};

arch/powerpc/Makefile

+17 −1
Original line number Diff line number Diff line
@@ -88,13 +88,30 @@ CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,-mminimal-toc) 
CFLAGS-$(CONFIG_PPC64)	+= $(call cc-option,-mno-pointers-to-nested-functions)

CFLAGS-$(CONFIG_PPC32)	:= -ffixed-r2 -mmultiple



ifeq ($(CONFIG_PPC_BOOK3S_64),y)

CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power7,-mtune=power4)

else

CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=powerpc64

endif



CFLAGS-$(CONFIG_CELL_CPU) += $(call cc-option,-mcpu=cell)

CFLAGS-$(CONFIG_POWER4_CPU) += $(call cc-option,-mcpu=power4)

CFLAGS-$(CONFIG_POWER5_CPU) += $(call cc-option,-mcpu=power5)

CFLAGS-$(CONFIG_POWER6_CPU) += $(call cc-option,-mcpu=power6)

CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7)



E5500_CPU := $(call cc-option,-mcpu=e500mc64,-mcpu=powerpc64)

CFLAGS-$(CONFIG_E5500_CPU) += $(E5500_CPU)

CFLAGS-$(CONFIG_E6500_CPU) += $(call cc-option,-mcpu=e6500,$(E5500_CPU))



ifeq ($(CONFIG_PPC32),y)

ifeq ($(CONFIG_PPC_E500MC),y)

CFLAGS-y += $(call cc-option,-mcpu=e500mc,-mcpu=powerpc)

else

CFLAGS-$(CONFIG_E500) += $(call cc-option,-mcpu=8540 -msoft-float,-mcpu=powerpc)

endif

endif



CFLAGS-$(CONFIG_TUNE_CELL) += $(call cc-option,-mtune=cell)



KBUILD_CPPFLAGS	+= -Iarch/$(ARCH)
@@ -139,7 +156,6 @@ endif 


cpu-as-$(CONFIG_4xx)		+= -Wa,-m405

cpu-as-$(CONFIG_ALTIVEC)	+= -Wa,-maltivec

cpu-as-$(CONFIG_E500)		+= -Wa,-me500

cpu-as-$(CONFIG_E200)		+= -Wa,-me200



KBUILD_AFLAGS += $(cpu-as-y)

arch/powerpc/boot/dts/c293pcie.dts

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/*

 * C293 PCIE Device Tree Source

 *

 * Copyright 2013 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



/include/ "fsl/c293si-pre.dtsi"



/ {

	model = "fsl,C293PCIE";

	compatible = "fsl,C293PCIE";



	memory {

		device_type = "memory";

	};



	ifc: ifc@fffe1e000 {

		reg = <0xf 0xffe1e000 0 0x2000>;

		ranges = <0x0 0x0 0xf 0xec000000 0x04000000

			  0x2 0x0 0xf 0xffdf0000 0x00010000>;



	};



	soc: soc@fffe00000 {

		ranges = <0x0 0xf 0xffe00000 0x100000>;

	};



	pci0: pcie@fffe0a000 {

		reg = <0xf 0xffe0a000 0 0x1000>;

		ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;

		pcie@0 {

			ranges = <0x2000000 0x0 0x80000000

				  0x2000000 0x0 0x80000000

				  0x0 0x20000000



				  0x1000000 0x0 0x0

				  0x1000000 0x0 0x0

				  0x0 0x100000>;

		};

	};

};



&ifc {

	nor@0,0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "cfi-flash";

		reg = <0x0 0x0 0x4000000>;

		bank-width = <2>;

		device-width = <1>;



		partition@0 {

			/* 1MB for DTB Image */

			reg = <0x0 0x00100000>;

			label = "NOR DTB Image";

		};



		partition@100000 {

			/* 8 MB for Linux Kernel Image */

			reg = <0x00100000 0x00800000>;

			label = "NOR Linux Kernel Image";

		};



		partition@900000 {

			/* 53MB for rootfs */

			reg = <0x00900000 0x03500000>;

			label = "NOR Rootfs Image";

		};



		partition@3e00000 {

			/* 1MB for blob encrypted key */

			reg = <0x03e00000 0x00100000>;

			label = "NOR blob encrypted key";

		};



		partition@3f00000 {

			/* 512KB for u-boot Bootloader Image and evn */

			reg = <0x03f00000 0x00100000>;

			label = "NOR U-Boot Image";

			read-only;

		};

	};



	nand@1,0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "fsl,ifc-nand";

		reg = <0x1 0x0 0x10000>;



		partition@0 {

			/* This location must not be altered  */

			/* 1MB for u-boot Bootloader Image */

			reg = <0x0 0x00100000>;

			label = "NAND U-Boot Image";

			read-only;

		};



		partition@100000 {

			/* 1MB for DTB Image */

			reg = <0x00100000 0x00100000>;

			label = "NAND DTB Image";

		};



		partition@200000 {

			/* 16MB for Linux Kernel Image */

			reg = <0x00200000 0x01000000>;

			label = "NAND Linux Kernel Image";

		};



		partition@1200000 {

			/* 4078MB for Root file System Image */

			reg = <0x00600000 0xfee00000>;

			label = "NAND RFS Image";

		};

	};



	cpld@2,0 {

		compatible = "fsl,c293pcie-cpld";

		reg = <0x2 0x0 0x20>;

	};

};



&soc {

	i2c@3000 {

		eeprom@50 {

			compatible = "st,24c1024";

			reg = <0x50>;

		};



		adt7461@4c {

			compatible = "adi,adt7461";

			reg = <0x4c>;

		};

	};



	spi@7000 {

		flash@0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "spansion,s25sl12801";

			reg = <0>;

			spi-max-frequency = <50000000>;



			partition@0 {

				/* 1MB for u-boot Bootloader Image */

				/* 1MB for Environment */

				reg = <0x0 0x00100000>;

				label = "SPI Flash U-Boot Image";

				read-only;

			};



			partition@100000 {

				/* 512KB for DTB Image */

				reg = <0x00100000 0x00080000>;

				label = "SPI Flash DTB Image";

			};



			partition@180000 {

				/* 4MB for Linux Kernel Image */

				reg = <0x00180000 0x00400000>;

				label = "SPI Flash Linux Kernel Image";

			};



			partition@580000 {

				/* 10.5MB for RFS Image */

				reg = <0x00580000 0x00a80000>;

				label = "SPI Flash RFS Image";

			};

		};

	};



	mdio@24000 {

		phy0: ethernet-phy@0 {

			interrupts = <2 1 0 0>;

			reg = <0x0>;

		};



		phy1: ethernet-phy@1 {

			interrupts = <2 1 0 0>;

			reg = <0x2>;

		};

	};



	enet0: ethernet@b0000 {

		phy-handle = <&phy0>;

		phy-connection-type = "rgmii-id";

	};



	enet1: ethernet@b1000 {

		phy-handle = <&phy1>;

		phy-connection-type = "rgmii-id";

	};

};

/include/ "fsl/c293si-post.dtsi"

arch/powerpc/boot/dts/fsl/c293si-post.dtsi

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/*

 * C293 Silicon/SoC Device Tree Source (post include)

 *

 * Copyright 2012 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



&ifc {

	#address-cells = <2>;

	#size-cells = <1>;

	compatible = "fsl,ifc", "simple-bus";

	interrupts = <19 2 0 0>;

};



/* controller at 0xa000 */

&pci0 {

	compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";

	device_type = "pci";

	#size-cells = <2>;

	#address-cells = <3>;

	bus-range = <0 255>;

	clock-frequency = <33333333>;

	interrupts = <16 2 0 0>;



	pcie@0 {

		reg = <0 0 0 0 0>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		device_type = "pci";

		interrupts = <16 2 0 0>;

		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <

			/* IDSEL 0x0 */

			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0

			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0

			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0

			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0

			>;

	};

};



&soc {

	#address-cells = <1>;

	#size-cells = <1>;

	device_type = "soc";

	compatible = "simple-bus";

	bus-frequency = <0>;		// Filled out by uboot.



	ecm-law@0 {

		compatible = "fsl,ecm-law";

		reg = <0x0 0x1000>;

		fsl,num-laws = <12>;

	};



	ecm@1000 {

		compatible = "fsl,c293-ecm", "fsl,ecm";

		reg = <0x1000 0x1000>;

		interrupts = <16 2 0 0>;

	};



	memory-controller@2000 {

		compatible = "fsl,c293-memory-controller";

		reg = <0x2000 0x1000>;

		interrupts = <16 2 0 0>;

	};



/include/ "pq3-i2c-0.dtsi"

/include/ "pq3-i2c-1.dtsi"

/include/ "pq3-duart-0.dtsi"

/include/ "pq3-espi-0.dtsi"

	spi0: spi@7000 {

		fsl,espi-num-chipselects = <1>;

	};



/include/ "pq3-gpio-0.dtsi"

	L2: l2-cache-controller@20000 {

		compatible = "fsl,c293-l2-cache-controller";

		reg = <0x20000 0x1000>;

		cache-line-size = <32>;	// 32 bytes

		cache-size = <0x80000>; // L2,512K

		interrupts = <16 2 0 0>;

	};



/include/ "pq3-dma-0.dtsi"

/include/ "pq3-esdhc-0.dtsi"

	sdhc@2e000 {

		compatible = "fsl,c293-esdhc", "fsl,esdhc";

		sdhci,auto-cmd12;

	};



	crypto@80000 {

/include/ "qoriq-sec6.0-0.dtsi"

	};



	crypto@80000 {

		reg = <0x80000 0x20000>;

		ranges = <0x0 0x80000 0x20000>;



		jr@1000{

			interrupts = <45 2 0 0>;

		};

		jr@2000{

			interrupts = <57 2 0 0>;

		};

	};



	crypto@a0000 {

/include/ "qoriq-sec6.0-0.dtsi"

	};



	crypto@a0000 {

		reg = <0xa0000 0x20000>;

		ranges = <0x0 0xa0000 0x20000>;



		jr@1000{

			interrupts = <49 2 0 0>;

		};

		jr@2000{

			interrupts = <50 2 0 0>;

		};

	};



	crypto@c0000 {

/include/ "qoriq-sec6.0-0.dtsi"

	};



	crypto@c0000 {

		reg = <0xc0000 0x20000>;

		ranges = <0x0 0xc0000 0x20000>;



		jr@1000{

			interrupts = <55 2 0 0>;

		};

		jr@2000{

			interrupts = <56 2 0 0>;

		};

	};



/include/ "pq3-mpic.dtsi"

/include/ "pq3-mpic-timer-B.dtsi"



/include/ "pq3-etsec2-0.dtsi"

	enet0: ethernet@b0000 {

		queue-group@b0000 {

			reg = <0x10000 0x1000>;

			fsl,rx-bit-map = <0xff>;

			fsl,tx-bit-map = <0xff>;

		};

	};



/include/ "pq3-etsec2-1.dtsi"

	enet1: ethernet@b1000 {

		queue-group@b1000 {

			reg = <0x11000 0x1000>;

			fsl,rx-bit-map = <0xff>;

			fsl,tx-bit-map = <0xff>;

		};

	};



	global-utilities@e0000 {

		compatible = "fsl,c293-guts";

		reg = <0xe0000 0x1000>;

		fsl,has-rstcr;

	};

};

arch/powerpc/boot/dts/fsl/c293si-pre.dtsi

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Original line number Diff line number Diff line 
/*

 * C293 Silicon/SoC Device Tree Source (pre include)

 *

 * Copyright 2012 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



/dts-v1/;



/include/ "e500v2_power_isa.dtsi"



/ {

	compatible = "fsl,C293";

	#address-cells = <2>;

	#size-cells = <2>;

	interrupt-parent = <&mpic>;



	aliases {

		serial0 = &serial0;

		serial1 = &serial1;

		ethernet0 = &enet0;

		ethernet1 = &enet1;

		pci0 = &pci0;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		PowerPC,e500v2@0 {

			device_type = "cpu";

			reg = <0x0>;

			next-level-cache = <&L2>;

		};

	};

};