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Commit 9cd4360d authored by Srikanth Thokala's avatar Srikanth Thokala Committed by Vinod Koul
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dma: Add Xilinx AXI Video Direct Memory Access Engine driver support 



This is the driver for the AXI Video Direct Memory Access (AXI
VDMA) core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type video target peripherals. The core provides efficient two
dimensional DMA operations with independent asynchronous read
and write channel operation.

This module works on Zynq (ARM Based SoC) and Microblaze platforms.

Signed-off-by: default avatarSrikanth Thokala <sthokal@xilinx.com>
Acked-by: default avatarJassi Brar <jassisinghbrar@gmail.com>
Reviewed-by: default avatarLevente Kurusa <levex@linux.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent eebeac03

drivers/dma/Kconfig

+14 −0
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@@ -361,6 +361,20 @@ config FSL_EDMA 
	  multiplexing capability for DMA request sources(slot).

	  This module can be found on Freescale Vybrid and LS-1 SoCs.



config XILINX_VDMA

	tristate "Xilinx AXI VDMA Engine"

	depends on (ARCH_ZYNQ || MICROBLAZE)

	select DMA_ENGINE

	help

	  Enable support for Xilinx AXI VDMA Soft IP.



	  This engine provides high-bandwidth direct memory access

	  between memory and AXI4-Stream video type target

	  peripherals including peripherals which support AXI4-

	  Stream Video Protocol.  It has two stream interfaces/

	  channels, Memory Mapped to Stream (MM2S) and Stream to

	  Memory Mapped (S2MM) for the data transfers.



config DMA_ENGINE

	bool

drivers/dma/Makefile

+1 −0
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@@ -46,3 +46,4 @@ obj-$(CONFIG_K3_DMA) += k3dma.o 
obj-$(CONFIG_MOXART_DMA) += moxart-dma.o

obj-$(CONFIG_FSL_EDMA) += fsl-edma.o

obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o

obj-y += xilinx/

drivers/dma/xilinx/Makefile

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obj-$(CONFIG_XILINX_VDMA) += xilinx_vdma.o

drivers/dma/xilinx/xilinx_vdma.c

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+1379 −0

File added.

Preview size limit exceeded, changes collapsed.

include/linux/amba/xilinx_dma.h

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/*

 * Xilinx DMA Engine drivers support header file

 *

 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.

 *

 * This is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef __DMA_XILINX_DMA_H

#define __DMA_XILINX_DMA_H



#include <linux/dma-mapping.h>

#include <linux/dmaengine.h>



/**

 * struct xilinx_vdma_config - VDMA Configuration structure

 * @frm_dly: Frame delay

 * @gen_lock: Whether in gen-lock mode

 * @master: Master that it syncs to

 * @frm_cnt_en: Enable frame count enable

 * @park: Whether wants to park

 * @park_frm: Frame to park on

 * @coalesc: Interrupt coalescing threshold

 * @delay: Delay counter

 * @reset: Reset Channel

 * @ext_fsync: External Frame Sync source

 */

struct xilinx_vdma_config {

	int frm_dly;

	int gen_lock;

	int master;

	int frm_cnt_en;

	int park;

	int park_frm;

	int coalesc;

	int delay;

	int reset;

	int ext_fsync;

};



int xilinx_vdma_channel_set_config(struct dma_chan *dchan,

					struct xilinx_vdma_config *cfg);



#endif