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Commit 9c4dea6b authored by Camus Wong's avatar Camus Wong Committed by Siddharth Zaveri
Browse files

clk: set NO_RATE_CACHE flag for all HDMI pixel clocks 



Since HDMI pixel clock is sourcing from MDSS internal PLL, all clocks
related to HDMI pixel clock chain need to always set rate even the
value is the same.

Change-Id: Ia311784788958598ca1e2a2bf75d9bae0ada5f83
Signed-off-by: default avatarCamus Wong <camusw@codeaurora.org>
parent 53d1dd96

drivers/clk/msm/clock-mmss-8996.c

+3 −0
Original line number Diff line number Diff line
@@ -1516,6 +1516,7 @@ static struct rcg_clk extpclk_clk_src = { 
		.ops = &clk_ops_byte,

		VDD_DIG_FMAX_MAP3(LOWER, 150000000, LOW, 300000000,

							NOMINAL, 600000000),

		.flags = CLKFLAG_NO_RATE_CACHE,

		CLK_INIT(extpclk_clk_src.c),

	},

};
@@ -2529,6 +2530,7 @@ static struct branch_clk mdss_extpclk_clk = { 
		.dbg_name = "mdss_extpclk_clk",

		.parent = &extpclk_clk_src.c,

		.ops = &clk_ops_branch,

		.flags = CLKFLAG_NO_RATE_CACHE,

		CLK_INIT(mdss_extpclk_clk.c),

	},

};
@@ -3740,6 +3742,7 @@ int msm_mmsscc_8996_probe(struct platform_device *pdev) 
	ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;

	ext_extpclk_clk_src.dev = &pdev->dev;

	ext_extpclk_clk_src.clk_id = "extpclk_src";

	ext_extpclk_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;



	efuse = readl_relaxed(gpu_base);

	gpu_speed_bin = ((efuse >> EFUSE_SHIFT_v3) & EFUSE_MASK_v3);

drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c

+1 −0
Original line number Diff line number Diff line
@@ -2519,6 +2519,7 @@ static struct hdmi_pll_vco_clk hdmi_vco_clk = { 
	.c = {

		.dbg_name = "hdmi_8996_vco_clk",

		.ops = &hdmi_8996_v1_vco_clk_ops,

		.flags = CLKFLAG_NO_RATE_CACHE,

		CLK_INIT(hdmi_vco_clk.c),

	},

};