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Commit 9c3a3009 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge tag 'omap-cleanup-b-for-3.5' of... 

Merge tag 'omap-cleanup-b-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into cleanup-hwmod

Clean up various aspects of the OMAP hwmod code, which is the IP block
control code for OMAP SoCs.  In particular, this series results in
a considerable diffstat savings by changing the way that IP block
interconnections are defined.
parents e816b57a 3af35fbc

arch/arm/mach-omap2/omap_hwmod.c

+893 −267

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-omap2/omap_hwmod_2420_data.c

+233 −1330

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-omap2/omap_hwmod_2430_data.c

+569 −1747

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arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c

+255 −11
Original line number Diff line number Diff line
@@ -15,10 +15,12 @@ 


#include <plat/omap_hwmod.h>

#include <plat/serial.h>

#include <plat/l3_2xxx.h>

#include <plat/l4_2xxx.h>



#include "omap_hwmod_common_data.h"



struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {

static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {

	{

		.pa_start	= OMAP2_UART1_BASE,

		.pa_end		= OMAP2_UART1_BASE + SZ_8K - 1,
@@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {

static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {

	{

		.pa_start	= OMAP2_UART2_BASE,

		.pa_end		= OMAP2_UART2_BASE + SZ_1K - 1,
@@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {

static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {

	{

		.pa_start	= OMAP2_UART3_BASE,

		.pa_end		= OMAP2_UART3_BASE + SZ_1K - 1,
@@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {

static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {

	{

		.pa_start	= 0x4802a000,

		.pa_end		= 0x4802a000 + SZ_1K - 1,
@@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {

static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {

	{

		.pa_start	= 0x48078000,

		.pa_end		= 0x48078000 + SZ_1K - 1,
@@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {

static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {

	{

		.pa_start	= 0x4807a000,

		.pa_end		= 0x4807a000 + SZ_1K - 1,
@@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {

static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {

	{

		.pa_start	= 0x4807c000,

		.pa_end		= 0x4807c000 + SZ_1K - 1,
@@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {

static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {

	{

		.pa_start	= 0x4807e000,

		.pa_end		= 0x4807e000 + SZ_1K - 1,
@@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {

static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {

	{

		.pa_start	= 0x48080000,

		.pa_end		= 0x48080000 + SZ_1K - 1,
@@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {

static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {

	{

		.pa_start	= 0x48082000,

		.pa_end		= 0x48082000 + SZ_1K - 1,
@@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { 
	{ }

};



struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {

static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {

	{

		.pa_start	= 0x48084000,

		.pa_end		= 0x48084000 + SZ_1K - 1,
@@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = { 
	{ }

};



/*

 * Common interconnect data

 */



/* L3 -> L4_CORE interface */

struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {

	.master	= &omap2xxx_l3_main_hwmod,

	.slave	= &omap2xxx_l4_core_hwmod,

	.user	= OCP_USER_MPU | OCP_USER_SDMA,

};



/* MPU -> L3 interface */

struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {

	.master = &omap2xxx_mpu_hwmod,

	.slave	= &omap2xxx_l3_main_hwmod,

	.user	= OCP_USER_MPU,

};



/* DSS -> l3 */

struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {

	.master		= &omap2xxx_dss_core_hwmod,

	.slave		= &omap2xxx_l3_main_hwmod,

	.fw = {

		.omap2 = {

			.l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,

			.flags	= OMAP_FIREWALL_L3,

		}

	},

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4_CORE -> L4_WKUP interface */

struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {

	.master	= &omap2xxx_l4_core_hwmod,

	.slave	= &omap2xxx_l4_wkup_hwmod,

	.user	= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4 CORE -> UART1 interface */

struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_uart1_hwmod,

	.clk		= "uart1_ick",

	.addr		= omap2xxx_uart1_addr_space,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4 CORE -> UART2 interface */

struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_uart2_hwmod,

	.clk		= "uart2_ick",

	.addr		= omap2xxx_uart2_addr_space,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4 PER -> UART3 interface */

struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_uart3_hwmod,

	.clk		= "uart3_ick",

	.addr		= omap2xxx_uart3_addr_space,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4 core -> mcspi1 interface */

struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_mcspi1_hwmod,

	.clk		= "mcspi1_ick",

	.addr		= omap2_mcspi1_addr_space,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4 core -> mcspi2 interface */

struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_mcspi2_hwmod,

	.clk		= "mcspi2_ick",

	.addr		= omap2_mcspi2_addr_space,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer2 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer2_hwmod,

	.clk		= "gpt2_ick",

	.addr		= omap2xxx_timer2_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer3 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer3_hwmod,

	.clk		= "gpt3_ick",

	.addr		= omap2xxx_timer3_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer4 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer4_hwmod,

	.clk		= "gpt4_ick",

	.addr		= omap2xxx_timer4_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer5 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer5_hwmod,

	.clk		= "gpt5_ick",

	.addr		= omap2xxx_timer5_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer6 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer6_hwmod,

	.clk		= "gpt6_ick",

	.addr		= omap2xxx_timer6_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer7 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer7_hwmod,

	.clk		= "gpt7_ick",

	.addr		= omap2xxx_timer7_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer8 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer8_hwmod,

	.clk		= "gpt8_ick",

	.addr		= omap2xxx_timer8_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer9 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer9_hwmod,

	.clk		= "gpt9_ick",

	.addr		= omap2xxx_timer9_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer10 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer10_hwmod,

	.clk		= "gpt10_ick",

	.addr		= omap2_timer10_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer11 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer11_hwmod,

	.clk		= "gpt11_ick",

	.addr		= omap2_timer11_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> timer12 */

struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_timer12_hwmod,

	.clk		= "gpt12_ick",

	.addr		= omap2xxx_timer12_addrs,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> dss */

struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_dss_core_hwmod,

	.clk		= "dss_ick",

	.addr		= omap2_dss_addrs,

	.fw = {

		.omap2 = {

			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,

			.flags	= OMAP_FIREWALL_L4,

		}

	},

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> dss_dispc */

struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_dss_dispc_hwmod,

	.clk		= "dss_ick",

	.addr		= omap2_dss_dispc_addrs,

	.fw = {

		.omap2 = {

			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,

			.flags	= OMAP_FIREWALL_L4,

		}

	},

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> dss_rfbi */

struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_dss_rfbi_hwmod,

	.clk		= "dss_ick",

	.addr		= omap2_dss_rfbi_addrs,

	.fw = {

		.omap2 = {

			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,

			.flags	= OMAP_FIREWALL_L4,

		}

	},

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4_core -> dss_venc */

struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {

	.master		= &omap2xxx_l4_core_hwmod,

	.slave		= &omap2xxx_dss_venc_hwmod,

	.clk		= "dss_ick",

	.addr		= omap2_dss_venc_addrs,

	.fw = {

		.omap2 = {

			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,

			.flags	= OMAP_FIREWALL_L4,

		}

	},

	.flags		= OCPIF_SWSUP_IDLE,

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};

arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

+562 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
 */

#include <plat/omap_hwmod.h>

#include <plat/serial.h>

#include <plat/gpio.h>

#include <plat/dma.h>

#include <plat/dmtimer.h>

#include <plat/mcspi.h>
@@ -17,6 +18,8 @@ 
#include <mach/irqs.h>



#include "omap_hwmod_common_data.h"

#include "cm-regbits-24xx.h"

#include "prm-regbits-24xx.h"

#include "wd_timer.h"



struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
@@ -170,3 +173,562 @@ struct omap_hwmod_class omap2xxx_mcspi_class = { 
	.sysc	= &omap2xxx_mcspi_sysc,

	.rev	= OMAP2_MCSPI_REV,

};



/*

 * IP blocks

 */



/* L3 */

struct omap_hwmod omap2xxx_l3_main_hwmod = {

	.name		= "l3_main",

	.class		= &l3_hwmod_class,

	.flags		= HWMOD_NO_IDLEST,

};



/* L4 CORE */

struct omap_hwmod omap2xxx_l4_core_hwmod = {

	.name		= "l4_core",

	.class		= &l4_hwmod_class,

	.flags		= HWMOD_NO_IDLEST,

};



/* L4 WKUP */

struct omap_hwmod omap2xxx_l4_wkup_hwmod = {

	.name		= "l4_wkup",

	.class		= &l4_hwmod_class,

	.flags		= HWMOD_NO_IDLEST,

};



/* MPU */

struct omap_hwmod omap2xxx_mpu_hwmod = {

	.name		= "mpu",

	.class		= &mpu_hwmod_class,

	.main_clk	= "mpu_ck",

};



/* IVA2 */

struct omap_hwmod omap2xxx_iva_hwmod = {

	.name		= "iva",

	.class		= &iva_hwmod_class,

};



/* always-on timers dev attribute */

static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {

	.timer_capability       = OMAP_TIMER_ALWON,

};



/* pwm timers dev attribute */

static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {

	.timer_capability       = OMAP_TIMER_HAS_PWM,

};



/* timer1 */



struct omap_hwmod omap2xxx_timer1_hwmod = {

	.name		= "timer1",

	.mpu_irqs	= omap2_timer1_mpu_irqs,

	.main_clk	= "gpt1_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT1_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,

		},

	},

	.dev_attr	= &capability_alwon_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer2 */



struct omap_hwmod omap2xxx_timer2_hwmod = {

	.name		= "timer2",

	.mpu_irqs	= omap2_timer2_mpu_irqs,

	.main_clk	= "gpt2_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT2_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,

		},

	},

	.dev_attr	= &capability_alwon_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer3 */



struct omap_hwmod omap2xxx_timer3_hwmod = {

	.name		= "timer3",

	.mpu_irqs	= omap2_timer3_mpu_irqs,

	.main_clk	= "gpt3_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT3_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,

		},

	},

	.dev_attr	= &capability_alwon_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer4 */



struct omap_hwmod omap2xxx_timer4_hwmod = {

	.name		= "timer4",

	.mpu_irqs	= omap2_timer4_mpu_irqs,

	.main_clk	= "gpt4_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT4_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,

		},

	},

	.dev_attr	= &capability_alwon_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer5 */



struct omap_hwmod omap2xxx_timer5_hwmod = {

	.name		= "timer5",

	.mpu_irqs	= omap2_timer5_mpu_irqs,

	.main_clk	= "gpt5_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT5_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,

		},

	},

	.dev_attr	= &capability_alwon_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer6 */



struct omap_hwmod omap2xxx_timer6_hwmod = {

	.name		= "timer6",

	.mpu_irqs	= omap2_timer6_mpu_irqs,

	.main_clk	= "gpt6_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT6_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,

		},

	},

	.dev_attr	= &capability_alwon_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer7 */



struct omap_hwmod omap2xxx_timer7_hwmod = {

	.name		= "timer7",

	.mpu_irqs	= omap2_timer7_mpu_irqs,

	.main_clk	= "gpt7_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT7_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,

		},

	},

	.dev_attr	= &capability_alwon_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer8 */



struct omap_hwmod omap2xxx_timer8_hwmod = {

	.name		= "timer8",

	.mpu_irqs	= omap2_timer8_mpu_irqs,

	.main_clk	= "gpt8_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT8_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,

		},

	},

	.dev_attr	= &capability_alwon_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer9 */



struct omap_hwmod omap2xxx_timer9_hwmod = {

	.name		= "timer9",

	.mpu_irqs	= omap2_timer9_mpu_irqs,

	.main_clk	= "gpt9_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT9_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,

		},

	},

	.dev_attr	= &capability_pwm_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer10 */



struct omap_hwmod omap2xxx_timer10_hwmod = {

	.name		= "timer10",

	.mpu_irqs	= omap2_timer10_mpu_irqs,

	.main_clk	= "gpt10_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT10_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,

		},

	},

	.dev_attr	= &capability_pwm_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer11 */



struct omap_hwmod omap2xxx_timer11_hwmod = {

	.name		= "timer11",

	.mpu_irqs	= omap2_timer11_mpu_irqs,

	.main_clk	= "gpt11_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT11_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,

		},

	},

	.dev_attr	= &capability_pwm_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* timer12 */



struct omap_hwmod omap2xxx_timer12_hwmod = {

	.name		= "timer12",

	.mpu_irqs	= omap2xxx_timer12_mpu_irqs,

	.main_clk	= "gpt12_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPT12_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,

		},

	},

	.dev_attr	= &capability_pwm_dev_attr,

	.class		= &omap2xxx_timer_hwmod_class,

};



/* wd_timer2 */

struct omap_hwmod omap2xxx_wd_timer2_hwmod = {

	.name		= "wd_timer2",

	.class		= &omap2xxx_wd_timer_hwmod_class,

	.main_clk	= "mpu_wdt_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,

		},

	},

};



/* UART1 */



struct omap_hwmod omap2xxx_uart1_hwmod = {

	.name		= "uart1",

	.mpu_irqs	= omap2_uart1_mpu_irqs,

	.sdma_reqs	= omap2_uart1_sdma_reqs,

	.main_clk	= "uart1_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_UART1_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,

		},

	},

	.class		= &omap2_uart_class,

};



/* UART2 */



struct omap_hwmod omap2xxx_uart2_hwmod = {

	.name		= "uart2",

	.mpu_irqs	= omap2_uart2_mpu_irqs,

	.sdma_reqs	= omap2_uart2_sdma_reqs,

	.main_clk	= "uart2_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_UART2_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,

		},

	},

	.class		= &omap2_uart_class,

};



/* UART3 */



struct omap_hwmod omap2xxx_uart3_hwmod = {

	.name		= "uart3",

	.mpu_irqs	= omap2_uart3_mpu_irqs,

	.sdma_reqs	= omap2_uart3_sdma_reqs,

	.main_clk	= "uart3_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 2,

			.module_bit = OMAP24XX_EN_UART3_SHIFT,

			.idlest_reg_id = 2,

			.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,

		},

	},

	.class		= &omap2_uart_class,

};



/* dss */



static struct omap_hwmod_opt_clk dss_opt_clks[] = {

	/*

	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core

	 * driver does not use these clocks.

	 */

	{ .role = "tv_clk", .clk = "dss_54m_fck" },

	{ .role = "sys_clk", .clk = "dss2_fck" },

};



struct omap_hwmod omap2xxx_dss_core_hwmod = {

	.name		= "dss_core",

	.class		= &omap2_dss_hwmod_class,

	.main_clk	= "dss1_fck", /* instead of dss_fck */

	.sdma_reqs	= omap2xxx_dss_sdma_chs,

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_DSS1_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,

		},

	},

	.opt_clks	= dss_opt_clks,

	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),

	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,

};



struct omap_hwmod omap2xxx_dss_dispc_hwmod = {

	.name		= "dss_dispc",

	.class		= &omap2_dispc_hwmod_class,

	.mpu_irqs	= omap2_dispc_irqs,

	.main_clk	= "dss1_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_DSS1_SHIFT,

			.module_offs = CORE_MOD,

			.idlest_reg_id = 1,

			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,

		},

	},

	.flags		= HWMOD_NO_IDLEST,

	.dev_attr	= &omap2_3_dss_dispc_dev_attr

};



static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {

	{ .role = "ick", .clk = "dss_ick" },

};



struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {

	.name		= "dss_rfbi",

	.class		= &omap2_rfbi_hwmod_class,

	.main_clk	= "dss1_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_DSS1_SHIFT,

			.module_offs = CORE_MOD,

		},

	},

	.opt_clks	= dss_rfbi_opt_clks,

	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),

	.flags		= HWMOD_NO_IDLEST,

};



struct omap_hwmod omap2xxx_dss_venc_hwmod = {

	.name		= "dss_venc",

	.class		= &omap2_venc_hwmod_class,

	.main_clk	= "dss_54m_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_DSS1_SHIFT,

			.module_offs = CORE_MOD,

		},

	},

	.flags		= HWMOD_NO_IDLEST,

};



/* gpio dev_attr */

struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {

	.bank_width = 32,

	.dbck_flag = false,

};



/* gpio1 */

struct omap_hwmod omap2xxx_gpio1_hwmod = {

	.name		= "gpio1",

	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,

	.mpu_irqs	= omap2_gpio1_irqs,

	.main_clk	= "gpios_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,

		},

	},

	.class		= &omap2xxx_gpio_hwmod_class,

	.dev_attr	= &omap2xxx_gpio_dev_attr,

};



/* gpio2 */

struct omap_hwmod omap2xxx_gpio2_hwmod = {

	.name		= "gpio2",

	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,

	.mpu_irqs	= omap2_gpio2_irqs,

	.main_clk	= "gpios_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,

		},

	},

	.class		= &omap2xxx_gpio_hwmod_class,

	.dev_attr	= &omap2xxx_gpio_dev_attr,

};



/* gpio3 */

struct omap_hwmod omap2xxx_gpio3_hwmod = {

	.name		= "gpio3",

	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,

	.mpu_irqs	= omap2_gpio3_irqs,

	.main_clk	= "gpios_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,

		},

	},

	.class		= &omap2xxx_gpio_hwmod_class,

	.dev_attr	= &omap2xxx_gpio_dev_attr,

};



/* gpio4 */

struct omap_hwmod omap2xxx_gpio4_hwmod = {

	.name		= "gpio4",

	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,

	.mpu_irqs	= omap2_gpio4_irqs,

	.main_clk	= "gpios_fck",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,

		},

	},

	.class		= &omap2xxx_gpio_hwmod_class,

	.dev_attr	= &omap2xxx_gpio_dev_attr,

};



/* mcspi1 */

static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {

	.num_chipselect = 4,

};



struct omap_hwmod omap2xxx_mcspi1_hwmod = {

	.name		= "mcspi1",

	.mpu_irqs	= omap2_mcspi1_mpu_irqs,

	.sdma_reqs	= omap2_mcspi1_sdma_reqs,

	.main_clk	= "mcspi1_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,

		},

	},

	.class		= &omap2xxx_mcspi_class,

	.dev_attr	= &omap_mcspi1_dev_attr,

};



/* mcspi2 */

static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {

	.num_chipselect = 2,

};



struct omap_hwmod omap2xxx_mcspi2_hwmod = {

	.name		= "mcspi2",

	.mpu_irqs	= omap2_mcspi2_mpu_irqs,

	.sdma_reqs	= omap2_mcspi2_sdma_reqs,

	.main_clk	= "mcspi2_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,

		},

	},

	.class		= &omap2xxx_mcspi_class,

	.dev_attr	= &omap_mcspi2_dev_attr,

};