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Commit 9b5cedb3 authored by Shaoqing Liu's avatar Shaoqing Liu Committed by Xiaogang Cui
Browse files

ARM: dts: msm: add cti devices of processors for mdmfermium 



Add CoreSight CTI devices to device tree to allow CoreSight
CTI driver to manage them.

Change-Id: I2c70b70195b896ab187844f388d370e1f9e94d41
Signed-off-by: default avatarShaoqing Liu <shaoqingliu@codeaurora.org>
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent ff134c6d

arch/arm/boot/dts/qcom/mdmfermium-coresight.dtsi

+175 −2
Original line number Original line Diff line number Diff line
@@ -24,6 +24,7 @@ 
		coresight-id = <0>;

		coresight-id = <0>;

		coresight-name = "coresight-tmc-etr";

		coresight-name = "coresight-tmc-etr";

		coresight-nr-inports = <1>;

		coresight-nr-inports = <1>;

		coresight-ctis = <&cti0 &cti8>;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -59,6 +60,7 @@ 
		coresight-child-list = <&replicator>;

		coresight-child-list = <&replicator>;

		coresight-child-ports = <0>;

		coresight-child-ports = <0>;

		coresight-default-sink;

		coresight-default-sink;

		coresight-ctis = <&cti0 &cti8>;





		clocks = <&clock_gcc clk_qdss_clk>,

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

			 <&clock_gcc clk_qdss_a_clk>;
@@ -99,13 +101,184 @@ 
		clock-names = "core_clk", "core_a_clk";

		clock-names = "core_clk", "core_a_clk";

	};

	};





	cti0: cti@6010000 {

		compatible = "arm,coresight-cti";

		reg = <0x6010000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <5>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti1: cti@6011000 {

		compatible = "arm,coresight-cti";

		reg = <0x6011000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <6>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti2: cti@6012000 {

		compatible = "arm,coresight-cti";

		reg = <0x6012000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <7>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti3: cti@6013000 {

		compatible = "arm,coresight-cti";

		reg = <0x6013000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <8>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti4: cti@6014000 {

		compatible = "arm,coresight-cti";

		reg = <0x6014000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <9>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti5: cti@6015000 {

		compatible = "arm,coresight-cti";

		reg = <0x6015000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <10>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti6: cti@6016000 {

		compatible = "arm,coresight-cti";

		reg = <0x6016000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <11>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti7: cti@6017000 {

		compatible = "arm,coresight-cti";

		reg = <0x6017000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <12>;

		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti8: cti@6018000 {

		compatible = "arm,coresight-cti";

		reg = <0x6018000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <13>;

		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_cpu0: cti@6043000 {

		compatible = "arm,coresight-cti";

		reg = <0x6043000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <14>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

		coresight-cti-cpu = <&CPU0>;



		qcom,cti-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_rpm_cpu0: cti@603c000 {

		compatible = "arm,coresight-cti";

		reg = <0x603c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <15>;

		coresight-name = "coresight-cti-rpm-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_modem_cpu0: cti@6038000 {

		compatible = "arm,coresight-cti";

		reg = <0x6038000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <16>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	stm: stm@6002000 {

	stm: stm@6002000 {

		compatible = "arm,coresight-stm";

		compatible = "arm,coresight-stm";

		reg = <0x6002000 0x1000>,

		reg = <0x6002000 0x1000>,

		      <0x9280000 0x180000>;

		      <0x9280000 0x180000>;

		reg-names = "stm-base", "stm-data-base";

		reg-names = "stm-base", "stm-data-base";





		coresight-id = <5>;

		coresight-id = <17>;

		coresight-name = "coresight-stm";

		coresight-name = "coresight-stm";

		coresight-nr-inports = <0>;

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-outports = <0>;
@@ -122,7 +295,7 @@ 
		reg = <0x6001000 0x1000>;

		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";

		reg-names = "csr-base";





		coresight-id = <6>;

		coresight-id = <18>;

		coresight-name = "coresight-csr";

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;

		coresight-nr-inports = <0>;