Loading arch/arm/boot/dts/qcom/msm8996-v3.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -256,6 +256,16 @@ clock-names = "core_clk"; qcom,use-dma-zone; }; qcom,m4m-hwmon@6530000 { compatible = "qcom,m4m-hwmon"; reg = <0x6530000 0x160>; interrupts = <0 19 4>; qcom,counter-event-sel = <4 0x8000>, <5 0x4000>; qcom,target-dev = <&m4m_cache>; }; }; &clock_cpu { Loading arch/arm/boot/dts/qcom/msm8996.dtsi +0 −8 Original line number Diff line number Diff line Loading @@ -456,14 +456,6 @@ qcom,target-dev = <&cpubw>; }; qcom,m4m-hwmon { compatible = "qcom,m4m-hwmon"; reg = <0x6530000 0x160>; interrupts = <0 19 4>; qcom,counter-event-sel = <4 0x100>; qcom,target-dev = <&m4m_cache>; }; mincpubw: qcom,mincpubw { compatible = "qcom,devbw"; governor = "powersave"; Loading drivers/devfreq/m4m-hwmon.c +11 −2 Original line number Diff line number Diff line Loading @@ -50,6 +50,9 @@ #define CYC_CNTR_IDX 0 #define WASTED_CYC_CNTR_IDX 1 /* counter is 28-bit */ #define CNT_MAX 0x0FFFFFFFU struct m4m_counter { int idx; u32 event_mask; Loading Loading @@ -144,7 +147,7 @@ static unsigned long _mon_get_count(struct m4m_hwmon *m, } if (ov) cnt = U32_MAX - start + cur_cnt; cnt = CNT_MAX - start + cur_cnt; else cnt = cur_cnt - start; Loading @@ -160,7 +163,11 @@ static unsigned long mon_get_count(struct m4m_hwmon *m, static inline void mon_set_limit(struct m4m_hwmon *m, enum request_group grp, unsigned int limit) { u32 start = U32_MAX - limit; u32 start; if (limit >= CNT_MAX) limit = CNT_MAX; start = CNT_MAX - limit; writel_relaxed(start, EVCNTR(m, m->cntr[grp].idx)); m->cntr[grp].last_start = start; Loading Loading @@ -283,6 +290,7 @@ static int m4m_start_hwmon(struct cache_hwmon *hw, struct mrps_stats *mrps) mon_init(m); mon_disable(m); mon_disable_cycle_cntr(m); for (i = 0; i < m->num_cntr; i++) { mon_ov_clear(m, i); limit = mrps_to_count(mrps->mrps[i], sample_ms, 0); Loading @@ -290,6 +298,7 @@ static int m4m_start_hwmon(struct cache_hwmon *hw, struct mrps_stats *mrps) } mon_clear_cycle_cntr(m); mon_enable(m); mon_enable_cycle_cntr(m); return 0; } Loading Loading
arch/arm/boot/dts/qcom/msm8996-v3.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -256,6 +256,16 @@ clock-names = "core_clk"; qcom,use-dma-zone; }; qcom,m4m-hwmon@6530000 { compatible = "qcom,m4m-hwmon"; reg = <0x6530000 0x160>; interrupts = <0 19 4>; qcom,counter-event-sel = <4 0x8000>, <5 0x4000>; qcom,target-dev = <&m4m_cache>; }; }; &clock_cpu { Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +0 −8 Original line number Diff line number Diff line Loading @@ -456,14 +456,6 @@ qcom,target-dev = <&cpubw>; }; qcom,m4m-hwmon { compatible = "qcom,m4m-hwmon"; reg = <0x6530000 0x160>; interrupts = <0 19 4>; qcom,counter-event-sel = <4 0x100>; qcom,target-dev = <&m4m_cache>; }; mincpubw: qcom,mincpubw { compatible = "qcom,devbw"; governor = "powersave"; Loading
drivers/devfreq/m4m-hwmon.c +11 −2 Original line number Diff line number Diff line Loading @@ -50,6 +50,9 @@ #define CYC_CNTR_IDX 0 #define WASTED_CYC_CNTR_IDX 1 /* counter is 28-bit */ #define CNT_MAX 0x0FFFFFFFU struct m4m_counter { int idx; u32 event_mask; Loading Loading @@ -144,7 +147,7 @@ static unsigned long _mon_get_count(struct m4m_hwmon *m, } if (ov) cnt = U32_MAX - start + cur_cnt; cnt = CNT_MAX - start + cur_cnt; else cnt = cur_cnt - start; Loading @@ -160,7 +163,11 @@ static unsigned long mon_get_count(struct m4m_hwmon *m, static inline void mon_set_limit(struct m4m_hwmon *m, enum request_group grp, unsigned int limit) { u32 start = U32_MAX - limit; u32 start; if (limit >= CNT_MAX) limit = CNT_MAX; start = CNT_MAX - limit; writel_relaxed(start, EVCNTR(m, m->cntr[grp].idx)); m->cntr[grp].last_start = start; Loading Loading @@ -283,6 +290,7 @@ static int m4m_start_hwmon(struct cache_hwmon *hw, struct mrps_stats *mrps) mon_init(m); mon_disable(m); mon_disable_cycle_cntr(m); for (i = 0; i < m->num_cntr; i++) { mon_ov_clear(m, i); limit = mrps_to_count(mrps->mrps[i], sample_ms, 0); Loading @@ -290,6 +298,7 @@ static int m4m_start_hwmon(struct cache_hwmon *hw, struct mrps_stats *mrps) } mon_clear_cycle_cntr(m); mon_enable(m); mon_enable_cycle_cntr(m); return 0; } Loading