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Commit 9a2ee715 authored by Sascha Hauer's avatar Sascha Hauer
Browse files

Merge branch 'cleanups/assorted' into imx-fixes-for-arnd 



Conflicts:
	arch/arm/mach-imx/mm-imx3.c

Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parents 13420c6b ca06679d

arch/arm/mach-imx/mm-imx3.c

+28 −25
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ 
static void imx3_idle(void)

{

	unsigned long reg = 0;



	if (!need_resched())

		__asm__ __volatile__(

			/* disable I and D cache */

			"mrc p15, 0, %0, c1, c0, 0\n"
@@ -56,6 +58,7 @@ static void imx3_idle(void) 
			"orr %0, %0, #0x00000004\n"

			"mcr p15, 0, %0, c1, c0, 0\n"

			: "=r" (reg));

	local_irq_enable();

}



static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@ -131,7 +134,7 @@ void __init imx31_init_early(void) 
{

	mxc_set_cpu_type(MXC_CPU_MX31);

	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));

	imx_idle = imx3_idle;

	pm_idle = imx3_idle;

	imx_ioremap = imx3_ioremap;

}
@@ -194,7 +197,7 @@ void __init imx35_init_early(void) 
	mxc_set_cpu_type(MXC_CPU_MX35);

	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));

	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));

	imx_idle = imx3_idle;

	pm_idle = imx3_idle;

	imx_ioremap = imx3_ioremap;

}

arch/arm/mach-mx5/cpu.c

+3 −2
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 
#include <linux/init.h>

#include <linux/module.h>

#include <mach/hardware.h>

#include <asm/io.h>

#include <linux/io.h>



static int mx5_cpu_rev = -1;
@@ -67,7 +67,8 @@ static int __init mx51_neon_fixup(void) 
	if (!cpu_is_mx51())

		return 0;



	if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {

	if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&

			(elf_hwcap & HWCAP_NEON)) {

		elf_hwcap &= ~HWCAP_NEON;

		pr_info("Turning off NEON support, detected broken NEON implementation\n");

	}

arch/arm/mach-mx5/mm.c

+4 −2
Original line number Diff line number Diff line
@@ -23,7 +23,9 @@ 


static void imx5_idle(void)

{

	if (!need_resched())

		mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);

	local_irq_enable();

}



/*
@@ -89,7 +91,7 @@ void __init imx51_init_early(void) 
	mxc_set_cpu_type(MXC_CPU_MX51);

	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));

	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));

	imx_idle = imx5_idle;

	pm_idle = imx5_idle;

}



void __init imx53_init_early(void)

arch/arm/plat-mxc/include/mach/common.h

+0 −1
Original line number Diff line number Diff line
@@ -85,7 +85,6 @@ enum mxc_cpu_pwr_mode { 
};



extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);

extern void (*imx_idle)(void);

extern void imx_print_silicon_rev(const char *cpu, int srev);



void avic_handle_irq(struct pt_regs *);

arch/arm/plat-mxc/include/mach/mxc.h

+0 −14
Original line number Diff line number Diff line
@@ -50,20 +50,6 @@ 
#define IMX_CHIP_REVISION_3_3		0x33

#define IMX_CHIP_REVISION_UNKNOWN	0xff



#define IMX_CHIP_REVISION_1_0_STRING		"1.0"

#define IMX_CHIP_REVISION_1_1_STRING		"1.1"

#define IMX_CHIP_REVISION_1_2_STRING		"1.2"

#define IMX_CHIP_REVISION_1_3_STRING		"1.3"

#define IMX_CHIP_REVISION_2_0_STRING		"2.0"

#define IMX_CHIP_REVISION_2_1_STRING		"2.1"

#define IMX_CHIP_REVISION_2_2_STRING		"2.2"

#define IMX_CHIP_REVISION_2_3_STRING		"2.3"

#define IMX_CHIP_REVISION_3_0_STRING		"3.0"

#define IMX_CHIP_REVISION_3_1_STRING		"3.1"

#define IMX_CHIP_REVISION_3_2_STRING		"3.2"

#define IMX_CHIP_REVISION_3_3_STRING		"3.3"

#define IMX_CHIP_REVISION_UNKNOWN_STRING	"unknown"



#ifndef __ASSEMBLY__

extern unsigned int __mxc_cpu_type;

#endif