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Commit 9a227f3f authored by Jaydeep Sen's avatar Jaydeep Sen
Browse files

clk: msm: 8937: Accomodate PLL setting changes for msm8937 



Msm8937 does not have a cci pll. Hence remove clock init for
a53cci_pll from common code and move it to 8952 specific clock
registrations. Also gpll0 is STROMER PLL for msm8937. Make changes
to reflect the same. Change efuse register address in msm8937 dtsi.

Change-Id: I7cbee0e529de97325564f7373439643b07956b6a
Signed-off-by: default avatarJaydeep Sen <jsen@codeaurora.org>
parent 55461996

arch/arm/boot/dts/qcom/msm8937.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -370,7 +370,7 @@ 
		reg =   <0xb111050 0x8>,

			<0xb011050 0x8>,

			<0xb1d1050 0x8>,

			<0x005c00c 0x8>;

			<0x00a412c 0x8>;

		reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",

			    "apcs-cci-rcg-base", "efuse";

		vdd-c0-supply = <&apc_vreg_corner>;
@@ -396,13 +396,14 @@ 
			<  998400000 1>,

			< 1094400000 2>,

			< 1248000000 3>,

			< 1401000000 4>;

			< 1344000000 4>,

			< 1401000000 5>;





		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 2>;

			<  533333333 3>;

		#clock-cells = <1>;

	};

drivers/clk/msm/clock-gcc-8952.c

+57 −12
Original line number Diff line number Diff line
@@ -294,7 +294,7 @@ static unsigned int soft_vote_gpll0; 
 * gets set from PLL voting FSM.It indicates when

 * FSM has enabled the PLL and PLL should be locked.

 */

static struct pll_vote_clk gpll0_clk_src = {

static struct pll_vote_clk gpll0_clk_src_8952 = {

	.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,

	.en_mask = BIT(0),

	.status_reg = (void __iomem *)GPLL0_STATUS,
@@ -305,12 +305,31 @@ static struct pll_vote_clk gpll0_clk_src = { 
	.c = {

		.parent = &xo_clk_src.c,

		.rate = 800000000,

		.dbg_name = "gpll0_clk_src",

		.dbg_name = "gpll0_clk_src_8952",

		.ops = &clk_ops_pll_acpu_vote,

		CLK_INIT(gpll0_clk_src.c),

		CLK_INIT(gpll0_clk_src_8952.c),

	},

};



static struct pll_vote_clk gpll0_clk_src_8937 = {

	.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,

	.en_mask = BIT(0),

	.status_reg = (void __iomem *)GPLL0_MODE,

	.status_mask = BIT(30),

	.soft_vote = &soft_vote_gpll0,

	.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,

	.base = &virt_bases[GCC_BASE],

	.c = {

		.parent = &xo_clk_src.c,

		.rate = 800000000,

		.dbg_name = "gpll0_clk_src_8937",

		.ops = &clk_ops_pll_acpu_vote,

		CLK_INIT(gpll0_clk_src_8937.c),

	},

};



DEFINE_EXT_CLK(gpll0_clk_src, NULL);

DEFINE_EXT_CLK(gpll0_ao_clk_src, NULL);

DEFINE_EXT_CLK(gpll0_out_aux_clk_src, &gpll0_clk_src.c);

DEFINE_EXT_CLK(gpll0_out_main_clk_src, &gpll0_clk_src.c);

DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
@@ -319,7 +338,7 @@ DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL); 
DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);



/* Don't vote for xo if using this clock to allow xo shutdown */

static struct pll_vote_clk gpll0_ao_clk_src = {

static struct pll_vote_clk gpll0_ao_clk_src_8952 = {

	.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,

	.en_mask = BIT(0),

	.status_reg = (void __iomem *)GPLL0_STATUS,
@@ -330,9 +349,26 @@ static struct pll_vote_clk gpll0_ao_clk_src = { 
	.c = {

		.parent = &xo_a_clk_src.c,

		.rate = 800000000,

		.dbg_name = "gpll0_ao_clk_src",

		.dbg_name = "gpll0_ao_clk_src_8952",

		.ops = &clk_ops_pll_acpu_vote,

		CLK_INIT(gpll0_ao_clk_src_8952.c),

	},

};



static struct pll_vote_clk gpll0_ao_clk_src_8937 = {

	.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,

	.en_mask = BIT(0),

	.status_reg = (void __iomem *)GPLL0_MODE,

	.status_mask = BIT(30),

	.soft_vote = &soft_vote_gpll0,

	.soft_vote_mask = PLL_SOFT_VOTE_ACPU,

	.base = &virt_bases[GCC_BASE],

	.c = {

		.parent = &xo_a_clk_src.c,

		.rate = 800000000,

		.dbg_name = "gpll0_ao_clk_src_8937",

		.ops = &clk_ops_pll_acpu_vote,

		CLK_INIT(gpll0_ao_clk_src.c),

		CLK_INIT(gpll0_ao_clk_src_8937.c),

	},

};
@@ -3520,7 +3556,6 @@ static struct mux_clk gcc_debug_mux_8937 = { 
		{ &gcc_crypto_axi_clk.c, 0x0139 },

		{ &gcc_crypto_ahb_clk.c, 0x013a },

		{ &gcc_bimc_gpu_clk.c, 0x0157 },

		{ &gcc_ipa_tbu_clk.c, 0x0198 },

		{ &gcc_vfe1_tbu_clk.c, 0x0199 },

		{ &gcc_camss_csi_vfe1_clk.c, 0x01a0 },

		{ &gcc_camss_vfe1_clk.c, 0x01a1 },
@@ -3583,9 +3618,6 @@ static struct clk_lookup msm_clocks_lookup_common[] = { 
	CLK_LIST(snoc_usb_clk),

	CLK_LIST(bimc_usb_clk),



	CLK_LIST(ipa_clk),

	CLK_LIST(ipa_a_clk),



	CLK_LIST(qdss_clk),

	CLK_LIST(qdss_a_clk),
@@ -3619,7 +3651,6 @@ static struct clk_lookup msm_clocks_lookup_common[] = { 
	CLK_LIST(gpll3_clk_src),

	CLK_LIST(a53ss_c0_pll),

	CLK_LIST(a53ss_c1_pll),

	CLK_LIST(a53ss_cci_pll),

	CLK_LIST(gcc_blsp1_ahb_clk),

	CLK_LIST(gcc_blsp2_ahb_clk),

	CLK_LIST(gcc_boot_rom_ahb_clk),
@@ -3789,6 +3820,11 @@ static struct clk_lookup msm_clocks_lookup_common[] = { 
};



static struct clk_lookup msm_clocks_lookup_8952[] = {

	CLK_LIST(a53ss_cci_pll),

	CLK_LIST(ipa_clk),

	CLK_LIST(ipa_a_clk),

	CLK_LIST(gpll0_clk_src_8952),

	CLK_LIST(gpll0_ao_clk_src_8952),

	CLK_LIST(gcc_oxili_gmem_clk),

	CLK_LIST(usb_fs_ic_clk_src),

	CLK_LIST(gcc_usb_fs_ic_clk),
@@ -3797,11 +3833,14 @@ static struct clk_lookup msm_clocks_lookup_8952[] = { 
	CLK_LIST(gcc_gfx_tcu_clk),

	CLK_LIST(gcc_gfx_tbu_clk),

	CLK_LIST(gcc_gtcu_ahb_clk),

	CLK_LIST(gcc_ipa_tbu_clk),

	CLK_LIST(gcc_usb_fs_ahb_clk),

	CLK_LIST(gcc_venus0_core1_vcodec0_clk),

};



static struct clk_lookup msm_clocks_lookup_8937[] = {

	CLK_LIST(gpll0_clk_src_8937),

	CLK_LIST(gpll0_ao_clk_src_8937),

	CLK_LIST(esc1_clk_src),

	CLK_LIST(gcc_mdss_esc1_clk),

	CLK_LIST(gcc_dcc_clk),
@@ -3977,8 +4016,14 @@ static int msm_gcc_probe(struct platform_device *pdev) 
	regval |= BIT(0);

	writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));



	if (compat_bin)

	if (compat_bin) {

		gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;

		gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;

		override_for_8937();

	} else {

		gpll0_clk_src.c.parent = &gpll0_clk_src_8952.c;

		gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8952.c;

	}



	ret = of_msm_clock_register(pdev->dev.of_node,

				msm_clocks_lookup_common,

include/dt-bindings/clock/msm-clocks-8952.h

+4 −0
Original line number Diff line number Diff line
@@ -16,6 +16,10 @@ 
/* clock_gcc controlled clocks */



/* GPLLs */

#define clk_gpll0_clk_src_8952			0x1617c790

#define clk_gpll0_ao_clk_src_8952		0x9b4db4e8

#define clk_gpll0_clk_src_8937			0x94350fc4

#define clk_gpll0_ao_clk_src_8937		0x923c7546

#define clk_gpll0_clk_src			0x5933b69f

#define clk_gpll0_ao_clk_src			0x6b2fb034

#define clk_gpll0_out_main			0x850fecec

include/dt-bindings/clock/msm-clocks-hwio-8952.h

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#ifndef __MSM_CLOCKS_8952_HWIO_H

#define __MSM_CLOCKS_8952_HWIO_H



#define GPLL0_MODE			0x21000

#define GPLL0_STATUS			0x2101C

#define GPLL6_STATUS			0x3701C

#define GPLL3_MODE			0x22000