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Commit 998850b1 authored by Rajesh Kemisetti's avatar Rajesh Kemisetti
Browse files

msm: kgsl: Enable content protection for A506 



Enable content protection for A506 from gpulist.

Also, skip scm call to program CP secure ucode base
registers since A506 supports retention for these
registers.

Change-Id: I48a0f04826430bfb927c755c176255be45199b26
Signed-off-by: default avatarRajesh Kemisetti <rajeshk@codeaurora.org>
parent 1c10389d

drivers/gpu/msm/adreno-gpulist.h

+4 −2
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2002,2007-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2002,2007-2016, The Linux Foundation. All rights reserved.

 *

 *

 * This program is free software; you can redistribute it and/or modify

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * it under the terms of the GNU General Public License version 2 and
@@ -216,9 +216,11 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 0,

		.major = 0,

		.minor = 6,

		.minor = 6,

		.patchid = ANY_ID,

		.patchid = ANY_ID,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.pm4fw_name = "a530_pm4.fw",

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a506_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = (SZ_128K + SZ_8K),

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.num_protected_regs = 0x20,

drivers/gpu/msm/adreno.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -111,6 +111,8 @@ 
#define ADRENO_LM BIT(8)

#define ADRENO_LM BIT(8)

/* The core uses 64 bit GPU addresses */

/* The core uses 64 bit GPU addresses */

#define ADRENO_64BIT BIT(9)

#define ADRENO_64BIT BIT(9)

/* The GPU supports retention for cpz registers */

#define ADRENO_CPZ_RETENTION BIT(10)





/*

/*

 * Adreno GPU quirks - control bits for various workarounds

 * Adreno GPU quirks - control bits for various workarounds

drivers/gpu/msm/adreno_a5xx.c

+4 −2
Original line number Original line Diff line number Diff line
@@ -2484,9 +2484,11 @@ static int a5xx_microcode_load(struct adreno_device *adreno_dev, 




	/*

	/*

	 * Resume call to write the zap shader base address into the

	 * Resume call to write the zap shader base address into the

	 * appropriate register

	 * appropriate register,

	 * skip if retention is supported for the CPZ register

	 */

	 */

	if (zap_ucode_loaded) {

	if (zap_ucode_loaded && !(ADRENO_FEATURE(adreno_dev,

		ADRENO_CPZ_RETENTION))) {

		int ret;

		int ret;

		struct scm_desc desc = {0};

		struct scm_desc desc = {0};