Merge "clk: msm: clock: Add list_registers clk ops for certain clk types" (997eabd7) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/clk/msm/clock-alpha-pll.c

+24 −0

Original line number	Diff line number	Diff line
		@@ -756,12 +756,34 @@ static enum handoff alpha_pll_handoff(struct clk *c)
		return HANDOFF_ENABLED_CLK;
		}

		static void __iomem alpha_pll_list_registers(struct clk clk, int n,
		struct clk_register_data *regs, u32 size)
		{
		struct alpha_pll_clk *pll = to_alpha_pll_clk(clk);
		static struct clk_register_data data[] = {
		{"PLL_MODE", 0x0},
		{"PLL_L_VAL", 0x4},
		{"PLL_ALPHA_VAL", 0x8},
		{"PLL_ALPHA_VAL_U", 0xC},
		{"PLL_USER_CTL", 0x10},
		{"PLL_CONFIG_CTL", 0x18},
		};

		if (n)
		return ERR_PTR(-EINVAL);

		*regs = data;
		*size = ARRAY_SIZE(data);
		return MODE_REG(pll);
		}

		struct clk_ops clk_ops_alpha_pll = {
		.enable = alpha_pll_enable,
		.disable = alpha_pll_disable,
		.round_rate = alpha_pll_round_rate,
		.set_rate = alpha_pll_set_rate,
		.handoff = alpha_pll_handoff,
		.list_registers = alpha_pll_list_registers,
		};

		struct clk_ops clk_ops_alpha_pll_hwfsm = {
		@@ -770,12 +792,14 @@ struct clk_ops clk_ops_alpha_pll_hwfsm = {
		.round_rate = alpha_pll_round_rate,
		.set_rate = alpha_pll_set_rate,
		.handoff = alpha_pll_handoff,
		.list_registers = alpha_pll_list_registers,
		};

		struct clk_ops clk_ops_fixed_alpha_pll = {
		.enable = alpha_pll_enable,
		.disable = alpha_pll_disable,
		.handoff = alpha_pll_handoff,
		.list_registers = alpha_pll_list_registers,
		};

		struct clk_ops clk_ops_dyna_alpha_pll = {

+33 −0

Original line number	Diff line number	Diff line
		@@ -1521,6 +1521,22 @@ static int reset_clk_rst(struct clk *c, enum clk_reset_action action)
		return __branch_clk_reset(RST_REG(rst), action);
		}

		static void __iomem reset_clk_list_registers(struct clk clk, int n,
		struct clk_register_data *regs, u32 size)
		{
		struct reset_clk *rst = to_reset_clk(clk);
		static struct clk_register_data data[] = {
		{"BCR", 0x0},
		};

		if (n)
		return ERR_PTR(-EINVAL);

		*regs = data;
		*size = ARRAY_SIZE(data);
		return RST_REG(rst);
		}

		static DEFINE_SPINLOCK(mux_reg_lock);

		static int mux_reg_enable(struct mux_clk *clk)
		@@ -1586,6 +1602,21 @@ static bool mux_reg_is_enabled(struct mux_clk *clk)
		return !!(regval & clk->en_mask);
		}

		static void __iomem mux_clk_list_registers(struct mux_clk clk, int n,
		struct clk_register_data *regs, u32 size)
		{
		static struct clk_register_data data[] = {
		{"DEBUG_CLK_CTL", 0x0},
		};

		if (n)
		return ERR_PTR(-EINVAL);

		*regs = data;
		*size = ARRAY_SIZE(data);
		return *clk->base + clk->offset;
		}

		/* PLL post-divider setting for each divider value */
		static struct div_map postdiv_map[] = {
		{ 0x0, 1 },
		@@ -1865,6 +1896,7 @@ struct clk_ops clk_ops_empty;

		struct clk_ops clk_ops_rst = {
		.reset = reset_clk_rst,
		.list_registers = reset_clk_list_registers,
		};

		struct clk_ops clk_ops_rcg = {
		@@ -2005,6 +2037,7 @@ struct clk_mux_ops mux_reg_ops = {
		.set_mux_sel = mux_reg_set_mux_sel,
		.get_mux_sel = mux_reg_get_mux_sel,
		.is_enabled = mux_reg_is_enabled,
		.list_registers = mux_clk_list_registers,
		};

		struct clk_div_ops div_reg_ops = {