[ARM] 5532/1: Freescale STMP: register definitions [3/3] (98f420b2) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/mach-stmp378x/stmp378x.c

+61 −48

Original line number	Original line	Diff line number	Diff line
	@@ -47,25 +47,28 @@
	static void stmp378x_ack_irq(unsigned int irq)		static void stmp378x_ack_irq(unsigned int irq)
	{		{
	/* Tell ICOLL to release IRQ line */		/* Tell ICOLL to release IRQ line */
	HW_ICOLL_VECTOR_WR(0x0);		__raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);

	/* ACK current interrupt */		/* ACK current interrupt */
	HW_ICOLL_LEVELACK_WR(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0);		__raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
			REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);

	/* Barrier */		/* Barrier */
	(void) HW_ICOLL_STAT_RD();		(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
	}		}

	static void stmp378x_mask_irq(unsigned int irq)		static void stmp378x_mask_irq(unsigned int irq)
	{		{
	/* IRQ disable */		/* IRQ disable */
	HW_ICOLL_INTERRUPTn_CLR(irq, BM_ICOLL_INTERRUPTn_ENABLE);		stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
			REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
	}		}

	static void stmp378x_unmask_irq(unsigned int irq)		static void stmp378x_unmask_irq(unsigned int irq)
	{		{
	/* IRQ enable */		/* IRQ enable */
	HW_ICOLL_INTERRUPTn_SET(irq, BM_ICOLL_INTERRUPTn_ENABLE);		stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
			REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
	}		}

	static struct irq_chip stmp378x_chip = {		static struct irq_chip stmp378x_chip = {
	@@ -84,52 +87,63 @@ void __init stmp378x_init_irq(void)
	*/		*/
	void stmp3xxx_arch_dma_enable_interrupt(int channel)		void stmp3xxx_arch_dma_enable_interrupt(int channel)
	{		{
	int dmabus = channel / 16;		void __iomem c1, c2;

	switch (dmabus) {		switch (STMP3XXX_DMA_BUS(channel)) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	HW_APBH_CTRL1_SET(1 << (16 + (channel % 16)));		c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
	HW_APBH_CTRL2_SET(1 << (16 + (channel % 16)));		c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
	break;		break;

	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	HW_APBX_CTRL1_SET(1 << (16 + (channel % 16)));		c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
	HW_APBX_CTRL2_SET(1 << (16 + (channel % 16)));		c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
	break;		break;

			default:
			return;
	}		}
			stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
			stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
	}		}
	EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);		EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);

	void stmp3xxx_arch_dma_clear_interrupt(int channel)		void stmp3xxx_arch_dma_clear_interrupt(int channel)
	{		{
	int dmabus = channel / 16;		void __iomem c1, c2;

	switch (dmabus) {		switch (STMP3XXX_DMA_BUS(channel)) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	HW_APBH_CTRL1_CLR(1 << (channel % 16));		c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
	HW_APBH_CTRL2_CLR(1 << (channel % 16));		c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
	break;		break;

	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	HW_APBX_CTRL1_CLR(1 << (channel % 16));		c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
	HW_APBX_CTRL2_CLR(1 << (channel % 16));		c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
	break;		break;

			default:
			return;
	}		}
			stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
			stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
	}		}
	EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);		EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);

	int stmp3xxx_arch_dma_is_interrupt(int channel)		int stmp3xxx_arch_dma_is_interrupt(int channel)
	{		{
	int dmabus = channel / 16;
	int r = 0;		int r = 0;

	switch (dmabus) {		switch (STMP3XXX_DMA_BUS(channel)) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	r = HW_APBH_CTRL1_RD() & (1 << (channel % 16));		r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
			(1 << STMP3XXX_DMA_CHANNEL(channel));
	break;		break;

	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	r = HW_APBX_CTRL1_RD() & (1 << (channel % 16));		r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
			(1 << STMP3XXX_DMA_CHANNEL(channel));
	break;		break;
	}		}
	return r;		return r;
	@@ -138,42 +152,41 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);

	void stmp3xxx_arch_dma_reset_channel(int channel)		void stmp3xxx_arch_dma_reset_channel(int channel)
	{		{
	int dmabus = channel / 16;		unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
	unsigned chbit = 1 << (channel % 16);		void __iomem *c0;
			u32 mask;

	switch (dmabus) {		switch (STMP3XXX_DMA_BUS(channel)) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	/* Reset channel and wait for it to complete */		c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
	HW_APBH_CTRL0_SET(chbit <<		mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
	BP_APBH_CTRL0_RESET_CHANNEL);
	while (HW_APBH_CTRL0_RD() &
	(chbit << BP_APBH_CTRL0_RESET_CHANNEL))
	continue;
	break;		break;

	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	/* Reset channel and wait for it to complete */		c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
	HW_APBX_CHANNEL_CTRL_SET(		mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
	BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit));
	while (HW_APBX_CHANNEL_CTRL_RD() &
	BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit))
	continue;
	break;		break;
			default:
			return;
	}		}

			/* Reset channel and wait for it to complete */
			stmp3xxx_setl(mask, c0);
			while (__raw_readl(c0) & mask)
			cpu_relax();
	}		}
	EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);		EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);

	void stmp3xxx_arch_dma_freeze(int channel)		void stmp3xxx_arch_dma_freeze(int channel)
	{		{
	int dmabus = channel / 16;		unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
	unsigned chbit = 1 << (channel % 16);		u32 mask = 1 << chbit;

	switch (dmabus) {		switch (STMP3XXX_DMA_BUS(channel)) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	HW_APBH_CTRL0_SET(1<<chbit);		stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
	break;		break;
	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	HW_APBX_CHANNEL_CTRL_SET(1<<chbit);		stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
	break;		break;
	}		}
	}		}
	@@ -181,15 +194,15 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);

	void stmp3xxx_arch_dma_unfreeze(int channel)		void stmp3xxx_arch_dma_unfreeze(int channel)
	{		{
	int dmabus = channel / 16;		unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
	unsigned chbit = 1 << (channel % 16);		u32 mask = 1 << chbit;

	switch (dmabus) {		switch (STMP3XXX_DMA_BUS(channel)) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	HW_APBH_CTRL0_CLR(1<<chbit);		stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
	break;		break;
	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	HW_APBX_CHANNEL_CTRL_CLR(1<<chbit);		stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
	break;		break;
	}		}
	}		}
	@@ -201,7 +214,7 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
	*		*
	* Logical Physical		* Logical Physical
	* f0000000 80000000 On-chip registers		* f0000000 80000000 On-chip registers
	* f1000000 00000000 256k on-chip SRAM		* f1000000 00000000 32k on-chip SRAM
	*/		*/

	static struct map_desc stmp378x_io_desc[] __initdata = {		static struct map_desc stmp378x_io_desc[] __initdata = {

arch/arm/mach-stmp37xx/stmp37xx.c

+43 −41

Original line number	Original line	Diff line number	Diff line
	@@ -34,6 +34,7 @@
	#include <mach/stmp3xxx.h>		#include <mach/stmp3xxx.h>
	#include <mach/dma.h>		#include <mach/dma.h>

			#include <mach/platform.h>
	#include <mach/regs-icoll.h>		#include <mach/regs-icoll.h>
	#include <mach/regs-apbh.h>		#include <mach/regs-apbh.h>
	#include <mach/regs-apbx.h>		#include <mach/regs-apbx.h>
	@@ -45,25 +46,28 @@
	static void stmp37xx_ack_irq(unsigned int irq)		static void stmp37xx_ack_irq(unsigned int irq)
	{		{
	/* Disable IRQ */		/* Disable IRQ */
	HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8));		stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
			REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);

	/* ACK current interrupt */		/* ACK current interrupt */
	HW_ICOLL_LEVELACK_WR(1);		__raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);

	/* Barrier */		/* Barrier */
	(void) HW_ICOLL_STAT_RD();		(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
	}		}

	static void stmp37xx_mask_irq(unsigned int irq)		static void stmp37xx_mask_irq(unsigned int irq)
	{		{
	/* IRQ disable */		/* IRQ disable */
	HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8));		stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
			REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
	}		}

	static void stmp37xx_unmask_irq(unsigned int irq)		static void stmp37xx_unmask_irq(unsigned int irq)
	{		{
	/* IRQ enable */		/* IRQ enable */
	HW_ICOLL_PRIORITYn_SET(irq / 4, 0x04 << ((irq % 4) * 8));		stmp3xxx_setl(0x04 << ((irq % 4) * 8),
			REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
	}		}

	static struct irq_chip stmp37xx_chip = {		static struct irq_chip stmp37xx_chip = {
	@@ -82,15 +86,15 @@ void __init stmp37xx_init_irq(void)
	*/		*/
	void stmp3xxx_arch_dma_enable_interrupt(int channel)		void stmp3xxx_arch_dma_enable_interrupt(int channel)
	{		{
	int dmabus = channel / 16;		switch (STMP3XXX_DMA_BUS(channel)) {

	switch (dmabus) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	HW_APBH_CTRL1_SET(1 << (8 + (channel % 16)));		stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
			REGS_APBH_BASE + HW_APBH_CTRL1);
	break;		break;

	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	HW_APBX_CTRL1_SET(1 << (8 + (channel % 16)));		stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
			REGS_APBX_BASE + HW_APBX_CTRL1);
	break;		break;
	}		}
	}		}
	@@ -98,15 +102,15 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);

	void stmp3xxx_arch_dma_clear_interrupt(int channel)		void stmp3xxx_arch_dma_clear_interrupt(int channel)
	{		{
	int dmabus = channel / 16;		switch (STMP3XXX_DMA_BUS(channel)) {

	switch (dmabus) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	HW_APBH_CTRL1_CLR(1 << (channel % 16));		stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
			REGS_APBH_BASE + HW_APBH_CTRL1);
	break;		break;

	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	HW_APBX_CTRL1_CLR(1 << (channel % 16));		stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
			REGS_APBX_BASE + HW_APBX_CTRL1);
	break;		break;
	}		}
	}		}
	@@ -116,15 +120,15 @@ int stmp3xxx_arch_dma_is_interrupt(int channel)
	{		{
	int r = 0;		int r = 0;

	int dmabus = channel / 16;		switch (STMP3XXX_DMA_BUS(channel)) {

	switch (dmabus) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	r = HW_APBH_CTRL1_RD() & (1 << (channel % 16));		r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
			(1 << STMP3XXX_DMA_CHANNEL(channel));
	break;		break;

	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	r = HW_APBX_CTRL1_RD() & (1 << (channel % 16));		r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
			(1 << STMP3XXX_DMA_CHANNEL(channel));
	break;		break;
	}		}
	return r;		return r;
	@@ -133,24 +137,24 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);

	void stmp3xxx_arch_dma_reset_channel(int channel)		void stmp3xxx_arch_dma_reset_channel(int channel)
	{		{
	int dmabus = channel / 16;		unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
	unsigned chbit = 1 << (channel % 16);

	switch (dmabus) {		switch (STMP3XXX_DMA_BUS(channel)) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	/* Reset channel and wait for it to complete */		/* Reset channel and wait for it to complete */
	HW_APBH_CTRL0_SET(chbit << BP_APBH_CTRL0_RESET_CHANNEL);		stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
	while (HW_APBH_CTRL0_RD() &		REGS_APBH_BASE + HW_APBH_CTRL0);
			while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
	(chbit << BP_APBH_CTRL0_RESET_CHANNEL))		(chbit << BP_APBH_CTRL0_RESET_CHANNEL))
	continue;		cpu_relax();
	break;		break;

	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	/* Reset channel and wait for it to complete */		stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
	HW_APBX_CTRL0_SET(chbit << BP_APBX_CTRL0_RESET_CHANNEL);		REGS_APBX_BASE + HW_APBX_CTRL0);
	while (HW_APBX_CTRL0_RD() &		while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
	(chbit << BP_APBX_CTRL0_RESET_CHANNEL))		(chbit << BP_APBX_CTRL0_RESET_CHANNEL))
	continue;		cpu_relax();
	break;		break;
	}		}
	}		}
	@@ -158,15 +162,14 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);

	void stmp3xxx_arch_dma_freeze(int channel)		void stmp3xxx_arch_dma_freeze(int channel)
	{		{
	int dmabus = channel / 16;		unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
	unsigned chbit = 1 << (channel % 16);

	switch (dmabus) {		switch (STMP3XXX_DMA_BUS(channel)) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	HW_APBH_CTRL0_SET(1<<chbit);		stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
	break;		break;
	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	HW_APBX_CTRL0_SET(1<<chbit);		stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
	break;		break;
	}		}
	}		}
	@@ -174,15 +177,14 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);

	void stmp3xxx_arch_dma_unfreeze(int channel)		void stmp3xxx_arch_dma_unfreeze(int channel)
	{		{
	int dmabus = channel / 16;		unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
	unsigned chbit = 1 << (channel % 16);

	switch (dmabus) {		switch (STMP3XXX_DMA_BUS(channel)) {
	case STMP3XXX_BUS_APBH:		case STMP3XXX_BUS_APBH:
	HW_APBH_CTRL0_CLR(1<<chbit);		stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
	break;		break;
	case STMP3XXX_BUS_APBX:		case STMP3XXX_BUS_APBX:
	HW_APBX_CTRL0_CLR(1<<chbit);		stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
	break;		break;
	}		}
	}		}
	@@ -194,7 +196,7 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
	*		*
	* Logical Physical		* Logical Physical
	* f0000000 80000000 On-chip registers		* f0000000 80000000 On-chip registers
	* f1000000 00000000 256k on-chip SRAM		* f1000000 00000000 32k on-chip SRAM
	*/		*/
	static struct map_desc stmp37xx_io_desc[] __initdata = {		static struct map_desc stmp37xx_io_desc[] __initdata = {
	{		{

arch/arm/plat-stmp3xxx/clock.c

+95 −72

Original line number	Original line	Diff line number	Diff line
	@@ -15,6 +15,7 @@
	* http://www.opensource.org/licenses/gpl-license.html		* http://www.opensource.org/licenses/gpl-license.html
	* http://www.gnu.org/copyleft/gpl.html		* http://www.gnu.org/copyleft/gpl.html
	*/		*/
			#define DEBUG
	#include <linux/kernel.h>		#include <linux/kernel.h>
	#include <linux/module.h>		#include <linux/module.h>
	#include <linux/init.h>		#include <linux/init.h>
	@@ -27,6 +28,7 @@

	#include <asm/mach-types.h>		#include <asm/mach-types.h>
	#include <asm/clkdev.h>		#include <asm/clkdev.h>
			#include <mach/platform.h>
	#include <mach/regs-clkctrl.h>		#include <mach/regs-clkctrl.h>

	#include "clock.h"		#include "clock.h"
	@@ -187,8 +189,8 @@ static long lcdif_get_rate(struct clk *clk)
	div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;		div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
	if (div) {		if (div) {
	rate /= div;		rate /= div;
	div = (HW_CLKCTRL_FRAC_RD() & BM_CLKCTRL_FRAC_PIXFRAC) >>		div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
	BP_CLKCTRL_FRAC_PIXFRAC;		BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
	rate /= div;		rate /= div;
	}		}
	clk->rate = rate;		clk->rate = rate;
	@@ -263,15 +265,19 @@ static int lcdif_set_rate(struct clk *clk, u32 rate)
	lowest_result / 1000, lowest_result % 1000);		lowest_result / 1000, lowest_result % 1000);

	/* Program ref_pix phase fractional divider */		/* Program ref_pix phase fractional divider */
	HW_CLKCTRL_FRAC_WR((HW_CLKCTRL_FRAC_RD() & ~BM_CLKCTRL_FRAC_PIXFRAC) \|		reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
	BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv));		reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
			reg_val \|= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
			__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);

	/* Ungate PFD */		/* Ungate PFD */
	HW_CLKCTRL_FRAC_CLR(BM_CLKCTRL_FRAC_CLKGATEPIX);		stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
			REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);

	/* Program pix divider */		/* Program pix divider */
	reg_val = __raw_readl(clk->scale_reg);		reg_val = __raw_readl(clk->scale_reg);
	reg_val &= ~(BM_CLKCTRL_PIX_DIV \| BM_CLKCTRL_PIX_CLKGATE);		reg_val &= ~(BM_CLKCTRL_PIX_DIV \| BM_CLKCTRL_PIX_CLKGATE);
	reg_val \|= BF_CLKCTRL_PIX_DIV(lowest_div);		reg_val \|= BF(lowest_div, CLKCTRL_PIX_DIV);
	__raw_writel(reg_val, clk->scale_reg);		__raw_writel(reg_val, clk->scale_reg);

	/* Wait for divider update */		/* Wait for divider update */
	@@ -287,7 +293,9 @@ static int lcdif_set_rate(struct clk *clk, u32 rate)
	}		}

	/* Switch to ref_pix source */		/* Switch to ref_pix source */
	HW_CLKCTRL_CLKSEQ_CLR(BM_CLKCTRL_CLKSEQ_BYPASS_PIX);		reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
			reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
			__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);

	out:		out:
	return ret;		return ret;
	@@ -296,6 +304,8 @@ out:

	static int cpu_set_rate(struct clk *clk, u32 rate)		static int cpu_set_rate(struct clk *clk, u32 rate)
	{		{
			u32 reg_val;

	if (rate < 24000)		if (rate < 24000)
	return -EINVAL;		return -EINVAL;
	else if (rate == 24000) {		else if (rate == 24000) {
	@@ -344,7 +354,12 @@ static int cpu_set_rate(struct clk *clk, u32 rate)
	__raw_writel(1<<7, clk->scale_reg + 8);		__raw_writel(1<<7, clk->scale_reg + 8);
	/* write clkctrl_cpu */		/* write clkctrl_cpu */
	clk->saved_div = clkctrl_cpu;		clk->saved_div = clkctrl_cpu;
	HW_CLKCTRL_CPU_WR((HW_CLKCTRL_CPU_RD() & ~0x3f) \| clkctrl_cpu);
			reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
			reg_val &= ~0x3F;
			reg_val \|= clkctrl_cpu;
			__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);

	for (i = 10000; i; i--)		for (i = 10000; i; i--)
	if (!clk_is_busy(clk))		if (!clk_is_busy(clk))
	break;		break;
	@@ -364,7 +379,7 @@ static long cpu_get_rate(struct clk *clk)
	long rate = clk->parent->rate * 18;		long rate = clk->parent->rate * 18;

	rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;		rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
	rate /= HW_CLKCTRL_CPU_RD() & 0x3f;		rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
	rate = ((rate + 9) / 10) * 10;		rate = ((rate + 9) / 10) * 10;
	clk->rate = rate;		clk->rate = rate;

	@@ -411,7 +426,7 @@ static long emi_get_rate(struct clk *clk)
	long rate = clk->parent->rate * 18;		long rate = clk->parent->rate * 18;

	rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;		rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
	rate /= HW_CLKCTRL_EMI_RD() & 0x3f;		rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
	clk->rate = rate;		clk->rate = rate;

	return rate;		return rate;
	@@ -427,44 +442,52 @@ static int clkseq_set_parent(struct clk clk, struct clk parent)
	shift = 4;		shift = 4;

	if (clk->bypass_reg) {		if (clk->bypass_reg) {
	u32 hbus_mask = BM_CLKCTRL_HBUS_DIV_FRAC_EN \|		#ifdef CONFIG_ARCH_STMP378X
	BM_CLKCTRL_HBUS_DIV;		u32 hbus_val, cpu_val;

	if (clk == &cpu_clk && shift == 4) {		if (clk == &cpu_clk && shift == 4) {
	u32 hbus_val = HW_CLKCTRL_HBUS_RD();		hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
	u32 cpu_val = HW_CLKCTRL_CPU_RD();		HW_CLKCTRL_HBUS);
	hbus_val &= ~hbus_mask;		cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
	hbus_val \|= 1;		HW_CLKCTRL_CPU);

			hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN \|
			BM_CLKCTRL_HBUS_DIV);
	clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;		clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
	cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;		cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
	cpu_val \|= 1;		cpu_val \|= 1;
	__raw_writel(1 << clk->bypass_shift,
	clk->bypass_reg + shift);
	if (machine_is_stmp378x()) {		if (machine_is_stmp378x()) {
	HW_CLKCTRL_HBUS_WR(hbus_val);		__raw_writel(hbus_val,
	HW_CLKCTRL_CPU_WR(cpu_val);		REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
			__raw_writel(cpu_val,
			REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
	hclk.rate = 0;		hclk.rate = 0;
	}		}
	} else if (clk == &cpu_clk && shift == 8) {		} else if (clk == &cpu_clk && shift == 8) {
	u32 hbus_val = HW_CLKCTRL_HBUS_RD();		hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
	u32 cpu_val = HW_CLKCTRL_CPU_RD();		HW_CLKCTRL_HBUS);
	hbus_val &= ~hbus_mask;		cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
			HW_CLKCTRL_CPU);
			hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN \|
			BM_CLKCTRL_HBUS_DIV);
	hbus_val \|= 2;		hbus_val \|= 2;
	cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;		cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
	if (clk->saved_div)		if (clk->saved_div)
	cpu_val \|= clk->saved_div;		cpu_val \|= clk->saved_div;
	else		else
	cpu_val \|= 2;		cpu_val \|= 2;

	if (machine_is_stmp378x()) {		if (machine_is_stmp378x()) {
	HW_CLKCTRL_HBUS_WR(hbus_val);		__raw_writel(hbus_val,
	HW_CLKCTRL_CPU_WR(cpu_val);		REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
			__raw_writel(cpu_val,
			REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
	hclk.rate = 0;		hclk.rate = 0;
	}		}
	__raw_writel(1 << clk->bypass_shift,		}
	clk->bypass_reg + shift);		#endif
	} else		__raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
	__raw_writel(1 << clk->bypass_shift,
	clk->bypass_reg + shift);

	ret = 0;		ret = 0;
	}		}
	@@ -640,7 +663,7 @@ static struct clk osc_24M = {

	static struct clk pll_clk = {		static struct clk pll_clk = {
	.parent = &osc_24M,		.parent = &osc_24M,
	.enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
	.enable_shift = 16,		.enable_shift = 16,
	.enable_wait = 10,		.enable_wait = 10,
	.flags = FIXED_RATE \| ENABLED,		.flags = FIXED_RATE \| ENABLED,
	@@ -650,11 +673,11 @@ static struct clk pll_clk = {

	static struct clk cpu_clk = {		static struct clk cpu_clk = {
	.parent = &pll_clk,		.parent = &pll_clk,
	.scale_reg = HW_CLKCTRL_FRAC_ADDR,		.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
	.scale_shift = 0,		.scale_shift = 0,
	.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,		.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
	.bypass_shift = 7,		.bypass_shift = 7,
	.busy_reg = HW_CLKCTRL_CPU_ADDR,		.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
	.busy_bit = 28,		.busy_bit = 28,
	.flags = RATE_PROPAGATES \| ENABLED,		.flags = RATE_PROPAGATES \| ENABLED,
	.ops = &cpu_ops,		.ops = &cpu_ops,
	@@ -662,10 +685,10 @@ static struct clk cpu_clk = {

	static struct clk io_clk = {		static struct clk io_clk = {
	.parent = &pll_clk,		.parent = &pll_clk,
	.enable_reg = HW_CLKCTRL_FRAC_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
	.enable_shift = 31,		.enable_shift = 31,
	.enable_negate = 1,		.enable_negate = 1,
	.scale_reg = HW_CLKCTRL_FRAC_ADDR,		.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
	.scale_shift = 24,		.scale_shift = 24,
	.flags = RATE_PROPAGATES \| ENABLED,		.flags = RATE_PROPAGATES \| ENABLED,
	.ops = &io_ops,		.ops = &io_ops,
	@@ -673,10 +696,10 @@ static struct clk io_clk = {

	static struct clk hclk = {		static struct clk hclk = {
	.parent = &cpu_clk,		.parent = &cpu_clk,
	.scale_reg = HW_CLKCTRL_HBUS_ADDR,		.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
	.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,		.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
	.bypass_shift = 7,		.bypass_shift = 7,
	.busy_reg = HW_CLKCTRL_HBUS_ADDR,		.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
	.busy_bit = 29,		.busy_bit = 29,
	.flags = RATE_PROPAGATES \| ENABLED,		.flags = RATE_PROPAGATES \| ENABLED,
	.ops = &hbus_ops,		.ops = &hbus_ops,
	@@ -684,8 +707,8 @@ static struct clk hclk = {

	static struct clk xclk = {		static struct clk xclk = {
	.parent = &osc_24M,		.parent = &osc_24M,
	.scale_reg = HW_CLKCTRL_XBUS_ADDR,		.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
	.busy_reg = HW_CLKCTRL_XBUS_ADDR,		.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
	.busy_bit = 31,		.busy_bit = 31,
	.flags = RATE_PROPAGATES \| ENABLED,		.flags = RATE_PROPAGATES \| ENABLED,
	.ops = &xbus_ops,		.ops = &xbus_ops,
	@@ -693,7 +716,7 @@ static struct clk xclk = {

	static struct clk uart_clk = {		static struct clk uart_clk = {
	.parent = &xclk,		.parent = &xclk,
	.enable_reg = HW_CLKCTRL_XTAL_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
	.enable_shift = 31,		.enable_shift = 31,
	.enable_negate = 1,		.enable_negate = 1,
	.flags = ENABLED,		.flags = ENABLED,
	@@ -702,7 +725,7 @@ static struct clk uart_clk = {

	static struct clk audio_clk = {		static struct clk audio_clk = {
	.parent = &xclk,		.parent = &xclk,
	.enable_reg = HW_CLKCTRL_XTAL_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
	.enable_shift = 30,		.enable_shift = 30,
	.enable_negate = 1,		.enable_negate = 1,
	.ops = &min_ops,		.ops = &min_ops,
	@@ -710,7 +733,7 @@ static struct clk audio_clk = {

	static struct clk pwm_clk = {		static struct clk pwm_clk = {
	.parent = &xclk,		.parent = &xclk,
	.enable_reg = HW_CLKCTRL_XTAL_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
	.enable_shift = 29,		.enable_shift = 29,
	.enable_negate = 1,		.enable_negate = 1,
	.ops = &min_ops,		.ops = &min_ops,
	@@ -718,7 +741,7 @@ static struct clk pwm_clk = {

	static struct clk dri_clk = {		static struct clk dri_clk = {
	.parent = &xclk,		.parent = &xclk,
	.enable_reg = HW_CLKCTRL_XTAL_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
	.enable_shift = 28,		.enable_shift = 28,
	.enable_negate = 1,		.enable_negate = 1,
	.ops = &min_ops,		.ops = &min_ops,
	@@ -726,7 +749,7 @@ static struct clk dri_clk = {

	static struct clk digctl_clk = {		static struct clk digctl_clk = {
	.parent = &xclk,		.parent = &xclk,
	.enable_reg = HW_CLKCTRL_XTAL_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
	.enable_shift = 27,		.enable_shift = 27,
	.enable_negate = 1,		.enable_negate = 1,
	.ops = &min_ops,		.ops = &min_ops,
	@@ -734,7 +757,7 @@ static struct clk digctl_clk = {

	static struct clk timer_clk = {		static struct clk timer_clk = {
	.parent = &xclk,		.parent = &xclk,
	.enable_reg = HW_CLKCTRL_XTAL_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
	.enable_shift = 26,		.enable_shift = 26,
	.enable_negate = 1,		.enable_negate = 1,
	.flags = ENABLED,		.flags = ENABLED,
	@@ -743,13 +766,13 @@ static struct clk timer_clk = {

	static struct clk lcdif_clk = {		static struct clk lcdif_clk = {
	.parent = &pll_clk,		.parent = &pll_clk,
	.scale_reg = HW_CLKCTRL_PIX_ADDR,		.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
	.busy_reg = HW_CLKCTRL_PIX_ADDR,		.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
	.busy_bit = 29,		.busy_bit = 29,
	.enable_reg = HW_CLKCTRL_PIX_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
	.enable_shift = 31,		.enable_shift = 31,
	.enable_negate = 1,		.enable_negate = 1,
	.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,		.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
	.bypass_shift = 1,		.bypass_shift = 1,
	.flags = NEEDS_SET_PARENT,		.flags = NEEDS_SET_PARENT,
	.ops = &lcdif_ops,		.ops = &lcdif_ops,
	@@ -757,12 +780,12 @@ static struct clk lcdif_clk = {

	static struct clk ssp_clk = {		static struct clk ssp_clk = {
	.parent = &io_clk,		.parent = &io_clk,
	.scale_reg = HW_CLKCTRL_SSP_ADDR,		.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
	.busy_reg = HW_CLKCTRL_SSP_ADDR,		.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
	.busy_bit = 29,		.busy_bit = 29,
	.enable_reg = HW_CLKCTRL_SSP_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
	.enable_shift = 31,		.enable_shift = 31,
	.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,		.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
	.bypass_shift = 5,		.bypass_shift = 5,
	.enable_negate = 1,		.enable_negate = 1,
	.flags = NEEDS_SET_PARENT,		.flags = NEEDS_SET_PARENT,
	@@ -771,13 +794,13 @@ static struct clk ssp_clk = {

	static struct clk gpmi_clk = {		static struct clk gpmi_clk = {
	.parent = &io_clk,		.parent = &io_clk,
	.scale_reg = HW_CLKCTRL_GPMI_ADDR,		.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
	.busy_reg = HW_CLKCTRL_GPMI_ADDR,		.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
	.busy_bit = 29,		.busy_bit = 29,
	.enable_reg = HW_CLKCTRL_GPMI_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
	.enable_shift = 31,		.enable_shift = 31,
	.enable_negate = 1,		.enable_negate = 1,
	.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,		.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
	.bypass_shift = 4,		.bypass_shift = 4,
	.flags = NEEDS_SET_PARENT,		.flags = NEEDS_SET_PARENT,
	.ops = &std_ops,		.ops = &std_ops,
	@@ -785,7 +808,7 @@ static struct clk gpmi_clk = {

	static struct clk spdif_clk = {		static struct clk spdif_clk = {
	.parent = &pll_clk,		.parent = &pll_clk,
	.enable_reg = HW_CLKCTRL_SPDIF_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
	.enable_shift = 31,		.enable_shift = 31,
	.enable_negate = 1,		.enable_negate = 1,
	.ops = &min_ops,		.ops = &min_ops,
	@@ -793,14 +816,14 @@ static struct clk spdif_clk = {

	static struct clk emi_clk = {		static struct clk emi_clk = {
	.parent = &pll_clk,		.parent = &pll_clk,
	.enable_reg = HW_CLKCTRL_EMI_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
	.enable_shift = 31,		.enable_shift = 31,
	.enable_negate = 1,		.enable_negate = 1,
	.scale_reg = HW_CLKCTRL_FRAC_ADDR,		.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
	.scale_shift = 8,		.scale_shift = 8,
	.busy_reg = HW_CLKCTRL_EMI_ADDR,		.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
	.busy_bit = 28,		.busy_bit = 28,
	.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,		.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
	.bypass_shift = 6,		.bypass_shift = 6,
	.flags = ENABLED,		.flags = ENABLED,
	.ops = &emi_ops,		.ops = &emi_ops,
	@@ -808,37 +831,37 @@ static struct clk emi_clk = {

	static struct clk ir_clk = {		static struct clk ir_clk = {
	.parent = &io_clk,		.parent = &io_clk,
	.enable_reg = HW_CLKCTRL_IR_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
	.enable_shift = 31,		.enable_shift = 31,
	.enable_negate = 1,		.enable_negate = 1,
	.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,		.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
	.bypass_shift = 3,		.bypass_shift = 3,
	.ops = &min_ops,		.ops = &min_ops,
	};		};

	static struct clk saif_clk = {		static struct clk saif_clk = {
	.parent = &pll_clk,		.parent = &pll_clk,
	.scale_reg = HW_CLKCTRL_SAIF_ADDR,		.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
	.busy_reg = HW_CLKCTRL_SAIF_ADDR,		.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
	.busy_bit = 29,		.busy_bit = 29,
	.enable_reg = HW_CLKCTRL_SAIF_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
	.enable_shift = 31,		.enable_shift = 31,
	.enable_negate = 1,		.enable_negate = 1,
	.bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR,		.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
	.bypass_shift = 0,		.bypass_shift = 0,
	.ops = &std_ops,		.ops = &std_ops,
	};		};

	static struct clk usb_clk = {		static struct clk usb_clk = {
	.parent = &pll_clk,		.parent = &pll_clk,
	.enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR,		.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
	.enable_shift = 18,		.enable_shift = 18,
	.enable_negate = 1,		.enable_negate = 1,
	.ops = &min_ops,		.ops = &min_ops,
	};		};

	/* list of all the clocks */		/* list of all the clocks */
	static __initdata struct clk_lookup onchip_clks[] = {		static struct clk_lookup onchip_clks[] = {
	{		{
	.con_id = "osc_24M",		.con_id = "osc_24M",
	.clk = &osc_24M,		.clk = &osc_24M,

arch/arm/plat-stmp3xxx/core.c

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -20,6 +20,7 @@
	#include <linux/io.h>		#include <linux/io.h>

	#include <mach/stmp3xxx.h>		#include <mach/stmp3xxx.h>
			#include <mach/platform.h>
	#include <mach/dma.h>		#include <mach/dma.h>
	#include <mach/regs-clkctrl.h>		#include <mach/regs-clkctrl.h>

	@@ -121,7 +122,7 @@ struct platform_device stmp3xxx_dbguart = {
	void __init stmp3xxx_init(void)		void __init stmp3xxx_init(void)
	{		{
	/* Turn off auto-slow and other tricks */		/* Turn off auto-slow and other tricks */
	HW_CLKCTRL_HBUS_CLR(0x07f00000U);		stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);

	stmp3xxx_dma_init();		stmp3xxx_dma_init();
	}		}

arch/arm/plat-stmp3xxx/dma.c

+69 −68

File changed.

Preview size limit exceeded, changes collapsed.