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Commit 981657e2 authored by Taniya Das's avatar Taniya Das
Browse files

clk: msm: Add support for 600MHz for GPU clock 



GPU clock frequency has been updated for SDM450 to support 600MHz, add
support for the same to add a new GPU frequency table.

Change-Id: Id9c0d2a0a859715e1d08dcfbfa2c3793bebeb9bd
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 822fa236

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ Required properties: 
			"qcom,gpucc-8996-v3.0"

			"qcom,gpucc-8996-pro"

			"qcom,gcc-gfx-8953"

			"qcom,gcc-gfx-sdm450"

			"qcom,gcc-9650"

			"qcom,cc-debug-9650"

			"qcom,gcc-mdm9607"

drivers/clk/msm/clock-gcc-8953.c

+26 −0
Original line number Diff line number Diff line
@@ -391,6 +391,25 @@ static struct clk_freq_tbl ftbl_gfx3d_clk_src[] = { 
	F_END

};



static struct clk_freq_tbl ftbl_gfx3d_clk_src_sdm450[] = {

	F_MM(  19200000, FIXED_CLK_SRC,                  xo,    1,    0,     0),

	F_MM(  50000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    8,    0,     0),

	F_MM(  80000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    5,    0,     0),

	F_MM( 100000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    4,    0,     0),

	F_MM( 133330000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    3,    0,     0),

	F_MM( 160000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,  2.5,    0,     0),

	F_MM( 200000000, FIXED_CLK_SRC,  gpll0_main_div2_mm,    2,    0,     0),

	F_MM( 216000000, FIXED_CLK_SRC, gpll6_main_div2_gfx,  2.5,    0,     0),

	F_MM( 266670000, FIXED_CLK_SRC,               gpll0,    3,    0,     0),

	F_MM( 320000000, FIXED_CLK_SRC,               gpll0,  2.5,    0,     0),

	F_MM( 400000000, FIXED_CLK_SRC,               gpll0,    2,    0,     0),

	F_MM( 460800000, FIXED_CLK_SRC,       gpll4_out_aux,  2.5,    0,     0),

	F_MM( 510000000,    1020000000,               gpll3,    1,    0,     0),

	F_MM( 560000000,    1120000000,               gpll3,    1,    0,     0),

	F_MM( 600000000,    1200000000,               gpll3,    1,    0,     0),

	F_END

};



static struct rcg_clk gfx3d_clk_src = {

	.cmd_rcgr_reg = GFX3D_CMD_RCGR,

	.set_rate = set_rate_hid,
@@ -4032,6 +4051,7 @@ static int msm_gcc_gfx_probe(struct platform_device *pdev) 
	struct resource *res;

	int ret;

	u32 regval;

	bool compat_bin = false;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");

	if (!res) {
@@ -4053,6 +4073,11 @@ static int msm_gcc_gfx_probe(struct platform_device *pdev) 
		return PTR_ERR(vdd_gfx.regulator[0]);

	}



	compat_bin = of_device_is_compatible(pdev->dev.of_node,

							"qcom,gcc-gfx-sdm450");

	if (compat_bin)

		gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_sdm450;



	ret = of_get_fmax_vdd_class(pdev, &gcc_oxili_gfx3d_clk.c,

					"qcom,gfxfreq-corner");

	if (ret) {
@@ -4075,6 +4100,7 @@ static int msm_gcc_gfx_probe(struct platform_device *pdev) 


static struct of_device_id msm_clock_gfx_match_table[] = {

	{ .compatible = "qcom,gcc-gfx-8953" },

	{ .compatible = "qcom,gcc-gfx-sdm450" },

	{}

};