Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Altera SOCFPGA Clock Manager

Required properties:

- compatible : "altr,clk-mgr"

- reg : Should contain base address and length for Clock Manager

Example:

	 clkmgr@ffd04000 {

		compatible = "altr,clk-mgr";

		reg = <0xffd04000 0x1000>;

	};

Broadcom Kona Family timer

-----------------------------------------------------

This timer is used in the following Broadcom SoCs:

 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155

Required properties:

- compatible : "bcm,kona-timer"

- reg : Register range for the timer

- interrupts : interrupt for the timer

- clock-frequency: frequency that the clock operates

Example:

	timer@35006000 {

		compatible = "bcm,kona-timer";

		reg = <0x35006000 0x1000>;

		interrupts = <0x0 7 0x4>;

		clock-frequency = <32768>;

	};

Properties:

- compatible : Should at least contain "qcom,msm-timer". More specific

  properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general

  purpose timer and a debug timer respectively.

               properties specify which subsystem the timers are paired with.

- interrupts : Interrupt indicating a match event.

               "qcom,kpss-timer" - krait subsystem

               "qcom,scss-timer" - scorpion subsystem

- reg : Specifies the base address of the timer registers. The second region

  specifies an optional register used to configure the clock divider.

- interrupts : Interrupts for the the debug timer, the first general purpose

               timer, and optionally a second general purpose timer in that

               order.

- clock-frequency : The frequency of the timer in Hz.

- reg : Specifies the base address of the timer registers.

- clock-frequency : The frequency of the debug timer and the general purpose

                    timer(s) in Hz in that order.

Optional:

- cpu-offset : per-cpu offset used when the timer is accessed without the

  CPU remapping facilities. The offset is cpu-offset * cpu-nr.

               CPU remapping facilities. The offset is

               cpu-offset + (0x10000 * cpu-nr).

Example:

       timer@200a004 {

               compatible = "qcom,msm-gpt", "qcom,msm-timer";

               interrupts = <1 2 0x301>;

               reg = <0x0200a004 0x10>;

               clock-frequency = <32768>;

               cpu-offset = <0x40000>;

       };

       timer@200a024 {

               compatible = "qcom,msm-dgt", "qcom,msm-timer";

               interrupts = <1 3 0x301>;

               reg = <0x0200a024 0x10>,

                     <0x0200a034 0x4>;

               clock-frequency = <6750000>;

       timer@200a000 {

               compatible = "qcom,scss-timer", "qcom,msm-timer";

               interrupts = <1 1 0x301>,

                            <1 2 0x301>,

                            <1 3 0x301>;

               reg = <0x0200a000 0x100>;

               clock-frequency = <19200000>,

                                 <32768>;

               cpu-offset = <0x40000>;

       };

NVIDIA Tegra Power Management Controller (PMC)

Properties:

The PMC block interacts with an external Power Management Unit. The PMC

mostly controls the entry and exit of the system from different sleep

modes. It provides power-gating controllers for SoC and CPU power-islands.

Required properties:

- name : Should be pmc

- compatible : Should contain "nvidia,tegra<chip>-pmc".

- reg : Offset and length of the register set for the device

- clocks : Must contain an entry for each entry in clock-names.

- clock-names : Must include the following entries:

  "pclk" (The Tegra clock of that name),

  "clk32k_in" (The 32KHz clock input to Tegra).

Optional properties:

- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.

  The PMU is an external Power Management Unit, whose interrupt output

  signal is fed into the PMC. This signal is optionally inverted, and then

  fed into the ARM GIC. The PMC is not involved in the detection or

  handling of this interrupt signal, merely its inversion.

- nvidia,suspend-mode : The suspend mode that the platform should use.

  Valid values are 0, 1 and 2:

  0 (LP0): CPU + Core voltage off and DRAM in self-refresh

  1 (LP1): CPU voltage off and DRAM in self-refresh

  2 (LP2): CPU voltage off

- nvidia,core-power-req-active-high : Boolean, core power request active-high

- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high

- nvidia,combined-power-req : Boolean, combined power request for CPU & Core

- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)

			   is enabled.

Required properties when nvidia,suspend-mode is specified:

- nvidia,cpu-pwr-good-time : CPU power good time in uS.

- nvidia,cpu-pwr-off-time : CPU power off time in uS.

- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>

			      Core power good time in uS.

- nvidia,core-pwr-off-time : Core power off time in uS.

Required properties when nvidia,suspend-mode=<0>:

- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector

  The LP0 vector contains the warm boot code that is executed by AVP when

  resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7

  processor and always being the first boot processor when chip is power on

  or resume from deep sleep mode. When the system is resumed from the deep

  sleep mode, the warm boot code will restore some PLLs, clocks and then

  bring up CPU0 for resuming the system.

Example:

/ SoC dts including file

pmc@7000f400 {

	compatible = "nvidia,tegra20-pmc";

	reg = <0x7000e400 0x400>;

	clocks = <&tegra_car 110>, <&clk32k_in>;

	clock-names = "pclk", "clk32k_in";

	nvidia,invert-interrupt;

	nvidia,suspend-mode = <1>;

	nvidia,cpu-pwr-good-time = <2000>;

	nvidia,cpu-pwr-off-time = <100>;

	nvidia,core-pwr-good-time = <3845 3845>;

	nvidia,core-pwr-off-time = <458>;

	nvidia,core-power-req-active-high;

	nvidia,sys-clock-req-active-high;

	nvidia,lp0-vec = <0xbdffd000 0x2000>;

};

/ Tegra board dts file

{

	...

	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;

		clk32k_in: clock {

			compatible = "fixed-clock";

			reg=<0>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};

	...

};

Device Tree Clock bindings for Altera's SoCFPGA platform

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

- compatible : shall be one of the following:

	"altr,socfpga-pll-clock" - for a PLL clock

	"altr,socfpga-perip-clock" - The peripheral clock divided from the

		PLL clock.

- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.

- clocks : shall be the input parent clock phandle for the clock. This is

	either an oscillator or a pll output.

- #clock-cells : from common clock binding, shall be set to 0.

Optional properties:

- fixed-divider : If clocks have a fixed divider value, use this property.