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Commit 97a0c919 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: mdss: add vbif debug bus support in xlog"

parents 548ca241 6a2faffc
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+4 −0
Original line number Diff line number Diff line
@@ -396,6 +396,10 @@ struct mdss_data_type {

	struct debug_bus *dbg_bus;
	u32 dbg_bus_size;
	struct vbif_debug_bus *vbif_dbg_bus;
	u32 vbif_dbg_bus_size;
	struct vbif_debug_bus *nrt_vbif_dbg_bus;
	u32 nrt_vbif_dbg_bus_size;
	struct mdss_debug_inf debug_inf;
	bool mixer_switched;
	struct mdss_panel_cfg pan_cfg;
+8 −0
Original line number Diff line number Diff line
@@ -50,6 +50,14 @@ struct debug_bus {
	u32 test_id;
};

struct vbif_debug_bus {
	u32 disable_bus_addr;
	u32 block_bus_addr;
	u32 bit_offset;
	u32 block_cnt;
	u32 test_pnt_cnt;
};

#define MDSS_XLOG(...) mdss_xlog(__func__, __LINE__, MDSS_XLOG_DEFAULT, \
		##__VA_ARGS__, DATA_LIMITER)

+133 −4
Original line number Diff line number Diff line
@@ -61,7 +61,10 @@ struct mdss_dbg_xlog {
	struct mdss_debug_base *blk_arr[MDSS_DEBUG_BASE_MAX];
	bool work_panic;
	bool work_dbgbus;
	bool work_vbif_dbgbus;
	u32 *dbgbus_dump; /* address for the debug bus dump */
	u32 *vbif_dbgbus_dump; /* address for the vbif debug bus dump */
	u32 *nrt_vbif_dbgbus_dump; /* address for the nrt vbif debug bus dump */
} mdss_dbg_xlog;

static inline bool mdss_xlog_is_enabled(u32 flag)
@@ -266,11 +269,122 @@ static void mdss_dump_debug_bus(u32 bus_dump_flag,
			dump_addr[i*4 + 3] = status;
		}

		/* Disable debug bus once we are done */
		writel_relaxed(0, mdss_res->mdp_base + head->wr_addr);

	}
	mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF);

	pr_info("========End Debug bus=========\n");
}

static void __vbif_debug_bus(struct vbif_debug_bus *head,
	void __iomem *vbif_base, u32 *dump_addr, bool in_log)
{
	int i, j;
	u32 val;

	if (!dump_addr && !in_log)
		return;

	for (i = 0; i < head->block_cnt; i++) {
		writel_relaxed(1 << (i + head->bit_offset),
				vbif_base + head->block_bus_addr);
		/* make sure that current bus blcok enable */
		wmb();
		for (j = 0; j < head->test_pnt_cnt; j++) {
			writel_relaxed(j, vbif_base + head->block_bus_addr + 4);
			/* make sure that test point is enabled */
			wmb();
			val = readl_relaxed(vbif_base + MMSS_VBIF_TEST_BUS_OUT);
			if (dump_addr)
				*dump_addr++ = val;
			if (in_log)
				pr_err("arb/xin id=%d index=%d val=0x%x\n",
					i, j, val);
		}
	}
}

static void mdss_dump_vbif_debug_bus(u32 bus_dump_flag,
	u32 **dump_mem, bool real_time)
{
	struct mdss_data_type *mdata = mdss_mdp_get_mdata();
	bool in_log, in_mem;
	u32 *dump_addr = NULL;
	u32 value;
	struct vbif_debug_bus *head;
	phys_addr_t phys = 0;
	int i, list_size = 0;
	void __iomem *vbif_base;
	struct vbif_debug_bus *dbg_bus;
	u32 bus_size;

	if (real_time) {
		pr_info("======== VBIF Debug bus DUMP =========\n");
		vbif_base = mdata->vbif_io.base;
		dbg_bus = mdata->vbif_dbg_bus;
		bus_size = mdata->vbif_dbg_bus_size;
	} else {
		pr_info("======== NRT VBIF Debug bus DUMP =========\n");
		vbif_base = mdata->vbif_nrt_io.base;
		dbg_bus = mdata->nrt_vbif_dbg_bus;
		bus_size = mdata->nrt_vbif_dbg_bus_size;
	}

	if (!dbg_bus || !bus_size)
		return;

	/* allocate memory for each test point */
	for (i = 0; i < bus_size; i++) {
		head = dbg_bus + i;
		list_size += (head->block_cnt * head->test_pnt_cnt);
	}

	/* will keep in 4 bytes each entry*/
	list_size *= 4;

	in_log = (bus_dump_flag & MDSS_DBG_DUMP_IN_LOG);
	in_mem = (bus_dump_flag & MDSS_DBG_DUMP_IN_MEM);

	if (in_mem) {
		if (!(*dump_mem))
			*dump_mem = dma_alloc_coherent(&mdata->pdev->dev,
				list_size, &phys, GFP_KERNEL);

		if (*dump_mem) {
			dump_addr = *dump_mem;
			pr_info("bus dump_addr:%p size:%d\n",
				dump_addr, list_size);
		} else {
			in_mem = false;
			pr_err("dump_mem: allocation fails\n");
		}
	}

	mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON);

	value = readl_relaxed(vbif_base + MMSS_VBIF_CLKON);
	writel_relaxed(value | BIT(1), vbif_base + MMSS_VBIF_CLKON);

	/* make sure that vbif core is on */
	wmb();

	for (i = 0; i < bus_size; i++) {
		head = dbg_bus + i;

		writel_relaxed(0, vbif_base + head->disable_bus_addr);
		writel_relaxed(BIT(0), vbif_base + MMSS_VBIF_TEST_BUS_OUT_CTRL);
		/* make sure that other bus is off */
		wmb();

		__vbif_debug_bus(head, vbif_base, dump_addr, in_log);
		dump_addr += (head->block_cnt * head->test_pnt_cnt);
	}

	mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF);

	pr_info("========End VBIF Debug bus=========\n");
}

static void mdss_dump_reg(u32 reg_dump_flag,
@@ -433,7 +547,8 @@ struct mdss_debug_base *get_dump_blk_addr(const char *blk_name)
}

static void mdss_xlog_dump_array(struct mdss_debug_base *blk_arr[],
	u32 len, bool dead, const char *name, bool dump_dbgbus)
	u32 len, bool dead, const char *name, bool dump_dbgbus,
	bool dump_vbif_dbgbus)
{
	int i;

@@ -449,6 +564,14 @@ static void mdss_xlog_dump_array(struct mdss_debug_base *blk_arr[],
		mdss_dump_debug_bus(mdss_dbg_xlog.enable_dbgbus_dump,
			&mdss_dbg_xlog.dbgbus_dump);

	if (dump_vbif_dbgbus) {
		mdss_dump_vbif_debug_bus(mdss_dbg_xlog.enable_dbgbus_dump,
			&mdss_dbg_xlog.vbif_dbgbus_dump, true);

		mdss_dump_vbif_debug_bus(mdss_dbg_xlog.enable_dbgbus_dump,
			&mdss_dbg_xlog.nrt_vbif_dbgbus_dump, false);
	}

	if (dead && mdss_dbg_xlog.panic_on_err)
		panic(name);
}
@@ -459,14 +582,15 @@ static void xlog_debug_work(struct work_struct *work)
	mdss_xlog_dump_array(mdss_dbg_xlog.blk_arr,
		ARRAY_SIZE(mdss_dbg_xlog.blk_arr),
		mdss_dbg_xlog.work_panic, "xlog_workitem",
		mdss_dbg_xlog.work_dbgbus);
		mdss_dbg_xlog.work_dbgbus,
		mdss_dbg_xlog.work_vbif_dbgbus);
}

void mdss_xlog_tout_handler_default(bool queue, const char *name, ...)
{
	int i, index = 0;
	bool dead = false;
	bool dump_dbgbus = false;
	bool dump_dbgbus = false, dump_vbif_dbgbus = false;
	va_list args;
	char *blk_name = NULL;
	struct mdss_debug_base *blk_base = NULL;
@@ -499,6 +623,9 @@ void mdss_xlog_tout_handler_default(bool queue, const char *name, ...)
		if (!strcmp(blk_name, "dbg_bus"))
			dump_dbgbus = true;

		if (!strcmp(blk_name, "vbif_dbg_bus"))
			dump_vbif_dbgbus = true;

		if (!strcmp(blk_name, "panic"))
			dead = true;
	}
@@ -508,9 +635,11 @@ void mdss_xlog_tout_handler_default(bool queue, const char *name, ...)
		/* schedule work to dump later */
		mdss_dbg_xlog.work_panic = dead;
		mdss_dbg_xlog.work_dbgbus = dump_dbgbus;
		mdss_dbg_xlog.work_vbif_dbgbus = dump_vbif_dbgbus;
		schedule_work(&mdss_dbg_xlog.xlog_dump_work);
	} else {
		mdss_xlog_dump_array(blk_arr, blk_len, dead, name, dump_dbgbus);
		mdss_xlog_dump_array(blk_arr, blk_len, dead, name, dump_dbgbus,
			dump_vbif_dbgbus);
	}
}

+603 −0
Original line number Diff line number Diff line
@@ -22,6 +22,586 @@

#define BUF_DUMP_LAST_N 10

static struct debug_bus dbg_bus_8996[] = {

	/* Unpack 0 sspp 0*/
	{ 0x188, 50, 6 },
	{ 0x188, 60, 6 },
	{ 0x188, 54, 6 },
	{ 0x188, 64, 6 },
	{ 0x188, 70, 6 },
	{ 0x188, 85, 6 },
	/* Upack 0 sspp 1*/
	{ 0x298, 50, 6 },
	{ 0x298, 60, 6 },
	{ 0x298, 54, 6 },
	{ 0x298, 64, 6 },
	{ 0x298, 70, 6 },
	{ 0x298, 85, 6 },
	/* scheduler */
	{ 0x348, 130, 0 },
	{ 0x348, 130, 1 },
	{ 0x348, 130, 2 },
	{ 0x348, 130, 3 },
	{ 0x348, 130, 4 },
	{ 0x348, 130, 5 },

	/* fetch sspp0 */

	/* vig 0 */
	{ 0x188, 0, 0 },
	{ 0x188, 0, 1 },
	{ 0x188, 0, 2 },
	{ 0x188, 0, 3 },
	{ 0x188, 0, 4 },
	{ 0x188, 0, 5 },
	{ 0x188, 0, 6 },
	{ 0x188, 0, 7 },

	{ 0x188, 1, 0 },
	{ 0x188, 1, 1 },
	{ 0x188, 1, 2 },
	{ 0x188, 1, 3 },
	{ 0x188, 1, 4 },
	{ 0x188, 1, 5 },
	{ 0x188, 1, 6 },
	{ 0x188, 1, 7 },

	{ 0x188, 2, 0 },
	{ 0x188, 2, 1 },
	{ 0x188, 2, 2 },
	{ 0x188, 2, 3 },
	{ 0x188, 2, 4 },
	{ 0x188, 2, 5 },
	{ 0x188, 2, 6 },
	{ 0x188, 2, 7 },

	{ 0x188, 4, 0 },
	{ 0x188, 4, 1 },
	{ 0x188, 4, 2 },
	{ 0x188, 4, 3 },
	{ 0x188, 4, 4 },
	{ 0x188, 4, 5 },
	{ 0x188, 4, 6 },
	{ 0x188, 4, 7 },

	{ 0x188, 5, 0 },
	{ 0x188, 5, 1 },
	{ 0x188, 5, 2 },
	{ 0x188, 5, 3 },
	{ 0x188, 5, 4 },
	{ 0x188, 5, 5 },
	{ 0x188, 5, 6 },
	{ 0x188, 5, 7 },

	/* vig 2 */
	{ 0x188, 20, 0 },
	{ 0x188, 20, 1 },
	{ 0x188, 20, 2 },
	{ 0x188, 20, 3 },
	{ 0x188, 20, 4 },
	{ 0x188, 20, 5 },
	{ 0x188, 20, 6 },
	{ 0x188, 20, 7 },

	{ 0x188, 21, 0 },
	{ 0x188, 21, 1 },
	{ 0x188, 21, 2 },
	{ 0x188, 21, 3 },
	{ 0x188, 21, 4 },
	{ 0x188, 21, 5 },
	{ 0x188, 21, 6 },
	{ 0x188, 21, 7 },

	{ 0x188, 22, 0 },
	{ 0x188, 22, 1 },
	{ 0x188, 22, 2 },
	{ 0x188, 22, 3 },
	{ 0x188, 22, 4 },
	{ 0x188, 22, 5 },
	{ 0x188, 22, 6 },
	{ 0x188, 22, 7 },

	{ 0x188, 24, 0 },
	{ 0x188, 24, 1 },
	{ 0x188, 24, 2 },
	{ 0x188, 24, 3 },
	{ 0x188, 24, 4 },
	{ 0x188, 24, 5 },
	{ 0x188, 24, 6 },
	{ 0x188, 24, 7 },

	{ 0x188, 25, 0 },
	{ 0x188, 25, 1 },
	{ 0x188, 25, 2 },
	{ 0x188, 25, 3 },
	{ 0x188, 25, 4 },
	{ 0x188, 25, 5 },
	{ 0x188, 25, 6 },
	{ 0x188, 25, 7 },

	/* rgb 0 */
	{ 0x188, 10, 0 },
	{ 0x188, 10, 1 },
	{ 0x188, 10, 2 },
	{ 0x188, 10, 3 },
	{ 0x188, 10, 4 },
	{ 0x188, 10, 5 },
	{ 0x188, 10, 6 },
	{ 0x188, 10, 7 },

	{ 0x188, 11, 0 },
	{ 0x188, 11, 1 },
	{ 0x188, 11, 2 },
	{ 0x188, 11, 3 },
	{ 0x188, 11, 4 },
	{ 0x188, 11, 5 },
	{ 0x188, 11, 6 },
	{ 0x188, 11, 7 },

	{ 0x188, 12, 0 },
	{ 0x188, 12, 1 },
	{ 0x188, 12, 2 },
	{ 0x188, 12, 3 },
	{ 0x188, 12, 4 },
	{ 0x188, 12, 5 },
	{ 0x188, 12, 6 },
	{ 0x188, 12, 7 },

	{ 0x188, 14, 0 },
	{ 0x188, 14, 1 },
	{ 0x188, 14, 2 },
	{ 0x188, 14, 3 },
	{ 0x188, 14, 4 },
	{ 0x188, 14, 5 },
	{ 0x188, 14, 6 },
	{ 0x188, 14, 7 },

	{ 0x188, 15, 0 },
	{ 0x188, 15, 1 },
	{ 0x188, 15, 2 },
	{ 0x188, 15, 3 },
	{ 0x188, 15, 4 },
	{ 0x188, 15, 5 },
	{ 0x188, 15, 6 },
	{ 0x188, 15, 7 },

	/* rgb 2 */
	{ 0x188, 30, 0 },
	{ 0x188, 30, 1 },
	{ 0x188, 30, 2 },
	{ 0x188, 30, 3 },
	{ 0x188, 30, 4 },
	{ 0x188, 30, 5 },
	{ 0x188, 30, 6 },
	{ 0x188, 30, 7 },

	{ 0x188, 31, 0 },
	{ 0x188, 31, 1 },
	{ 0x188, 31, 2 },
	{ 0x188, 31, 3 },
	{ 0x188, 31, 4 },
	{ 0x188, 31, 5 },
	{ 0x188, 31, 6 },
	{ 0x188, 31, 7 },

	{ 0x188, 32, 0 },
	{ 0x188, 32, 1 },
	{ 0x188, 32, 2 },
	{ 0x188, 32, 3 },
	{ 0x188, 32, 4 },
	{ 0x188, 32, 5 },
	{ 0x188, 32, 6 },
	{ 0x188, 32, 7 },

	{ 0x188, 34, 0 },
	{ 0x188, 34, 1 },
	{ 0x188, 34, 2 },
	{ 0x188, 34, 3 },
	{ 0x188, 34, 4 },
	{ 0x188, 34, 5 },
	{ 0x188, 34, 6 },
	{ 0x188, 34, 7 },

	{ 0x188, 35, 0 },
	{ 0x188, 35, 1 },
	{ 0x188, 35, 2 },
	{ 0x188, 35, 3 },
	{ 0x188, 35, 4 },
	{ 0x188, 35, 5 },
	{ 0x188, 35, 6 },
	{ 0x188, 35, 7 },

	/* dma 0 */
	{ 0x188, 40, 0 },
	{ 0x188, 40, 1 },
	{ 0x188, 40, 2 },
	{ 0x188, 40, 3 },
	{ 0x188, 40, 4 },
	{ 0x188, 40, 5 },
	{ 0x188, 40, 6 },
	{ 0x188, 40, 7 },

	{ 0x188, 41, 0 },
	{ 0x188, 41, 1 },
	{ 0x188, 41, 2 },
	{ 0x188, 41, 3 },
	{ 0x188, 41, 4 },
	{ 0x188, 41, 5 },
	{ 0x188, 41, 6 },
	{ 0x188, 41, 7 },

	{ 0x188, 42, 0 },
	{ 0x188, 42, 1 },
	{ 0x188, 42, 2 },
	{ 0x188, 42, 3 },
	{ 0x188, 42, 4 },
	{ 0x188, 42, 5 },
	{ 0x188, 42, 6 },
	{ 0x188, 42, 7 },

	{ 0x188, 44, 0 },
	{ 0x188, 44, 1 },
	{ 0x188, 44, 2 },
	{ 0x188, 44, 3 },
	{ 0x188, 44, 4 },
	{ 0x188, 44, 5 },
	{ 0x188, 44, 6 },
	{ 0x188, 44, 7 },

	{ 0x188, 45, 0 },
	{ 0x188, 45, 1 },
	{ 0x188, 45, 2 },
	{ 0x188, 45, 3 },
	{ 0x188, 45, 4 },
	{ 0x188, 45, 5 },
	{ 0x188, 45, 6 },
	{ 0x188, 45, 7 },

	/* cursor 0 */
	{ 0x188, 80, 0 },
	{ 0x188, 80, 1 },
	{ 0x188, 80, 2 },
	{ 0x188, 80, 3 },
	{ 0x188, 80, 4 },
	{ 0x188, 80, 5 },
	{ 0x188, 80, 6 },
	{ 0x188, 80, 7 },

	{ 0x188, 81, 0 },
	{ 0x188, 81, 1 },
	{ 0x188, 81, 2 },
	{ 0x188, 81, 3 },
	{ 0x188, 81, 4 },
	{ 0x188, 81, 5 },
	{ 0x188, 81, 6 },
	{ 0x188, 81, 7 },

	{ 0x188, 82, 0 },
	{ 0x188, 82, 1 },
	{ 0x188, 82, 2 },
	{ 0x188, 82, 3 },
	{ 0x188, 82, 4 },
	{ 0x188, 82, 5 },
	{ 0x188, 82, 6 },
	{ 0x188, 82, 7 },

	{ 0x188, 83, 0 },
	{ 0x188, 83, 1 },
	{ 0x188, 83, 2 },
	{ 0x188, 83, 3 },
	{ 0x188, 83, 4 },
	{ 0x188, 83, 5 },
	{ 0x188, 83, 6 },
	{ 0x188, 83, 7 },

	{ 0x188, 84, 0 },
	{ 0x188, 84, 1 },
	{ 0x188, 84, 2 },
	{ 0x188, 84, 3 },
	{ 0x188, 84, 4 },
	{ 0x188, 84, 5 },
	{ 0x188, 84, 6 },
	{ 0x188, 84, 7 },

	/* fetch sspp1 */
	/* vig 1 */
	{ 0x298, 0, 0 },
	{ 0x298, 0, 1 },
	{ 0x298, 0, 2 },
	{ 0x298, 0, 3 },
	{ 0x298, 0, 4 },
	{ 0x298, 0, 5 },
	{ 0x298, 0, 6 },
	{ 0x298, 0, 7 },

	{ 0x298, 1, 0 },
	{ 0x298, 1, 1 },
	{ 0x298, 1, 2 },
	{ 0x298, 1, 3 },
	{ 0x298, 1, 4 },
	{ 0x298, 1, 5 },
	{ 0x298, 1, 6 },
	{ 0x298, 1, 7 },

	{ 0x298, 2, 0 },
	{ 0x298, 2, 1 },
	{ 0x298, 2, 2 },
	{ 0x298, 2, 3 },
	{ 0x298, 2, 4 },
	{ 0x298, 2, 5 },
	{ 0x298, 2, 6 },
	{ 0x298, 2, 7 },

	{ 0x298, 4, 0 },
	{ 0x298, 4, 1 },
	{ 0x298, 4, 2 },
	{ 0x298, 4, 3 },
	{ 0x298, 4, 4 },
	{ 0x298, 4, 5 },
	{ 0x298, 4, 6 },
	{ 0x298, 4, 7 },

	{ 0x298, 5, 0 },
	{ 0x298, 5, 1 },
	{ 0x298, 5, 2 },
	{ 0x298, 5, 3 },
	{ 0x298, 5, 4 },
	{ 0x298, 5, 5 },
	{ 0x298, 5, 6 },
	{ 0x298, 5, 7 },

	/* vig 3 */
	{ 0x298, 20, 0 },
	{ 0x298, 20, 1 },
	{ 0x298, 20, 2 },
	{ 0x298, 20, 3 },
	{ 0x298, 20, 4 },
	{ 0x298, 20, 5 },
	{ 0x298, 20, 6 },
	{ 0x298, 20, 7 },

	{ 0x298, 21, 0 },
	{ 0x298, 21, 1 },
	{ 0x298, 21, 2 },
	{ 0x298, 21, 3 },
	{ 0x298, 21, 4 },
	{ 0x298, 21, 5 },
	{ 0x298, 21, 6 },
	{ 0x298, 21, 7 },

	{ 0x298, 22, 0 },
	{ 0x298, 22, 1 },
	{ 0x298, 22, 2 },
	{ 0x298, 22, 3 },
	{ 0x298, 22, 4 },
	{ 0x298, 22, 5 },
	{ 0x298, 22, 6 },
	{ 0x298, 22, 7 },

	{ 0x298, 24, 0 },
	{ 0x298, 24, 1 },
	{ 0x298, 24, 2 },
	{ 0x298, 24, 3 },
	{ 0x298, 24, 4 },
	{ 0x298, 24, 5 },
	{ 0x298, 24, 6 },
	{ 0x298, 24, 7 },

	{ 0x298, 25, 0 },
	{ 0x298, 25, 1 },
	{ 0x298, 25, 2 },
	{ 0x298, 25, 3 },
	{ 0x298, 25, 4 },
	{ 0x298, 25, 5 },
	{ 0x298, 25, 6 },
	{ 0x298, 25, 7 },

	/* rgb 1 */
	{ 0x298, 10, 0 },
	{ 0x298, 10, 1 },
	{ 0x298, 10, 2 },
	{ 0x298, 10, 3 },
	{ 0x298, 10, 4 },
	{ 0x298, 10, 5 },
	{ 0x298, 10, 6 },
	{ 0x298, 10, 7 },

	{ 0x298, 11, 0 },
	{ 0x298, 11, 1 },
	{ 0x298, 11, 2 },
	{ 0x298, 11, 3 },
	{ 0x298, 11, 4 },
	{ 0x298, 11, 5 },
	{ 0x298, 11, 6 },
	{ 0x298, 11, 7 },

	{ 0x298, 12, 0 },
	{ 0x298, 12, 1 },
	{ 0x298, 12, 2 },
	{ 0x298, 12, 3 },
	{ 0x298, 12, 4 },
	{ 0x298, 12, 5 },
	{ 0x298, 12, 6 },
	{ 0x298, 12, 7 },

	{ 0x298, 14, 0 },
	{ 0x298, 14, 1 },
	{ 0x298, 14, 2 },
	{ 0x298, 14, 3 },
	{ 0x298, 14, 4 },
	{ 0x298, 14, 5 },
	{ 0x298, 14, 6 },
	{ 0x298, 14, 7 },

	{ 0x298, 15, 0 },
	{ 0x298, 15, 1 },
	{ 0x298, 15, 2 },
	{ 0x298, 15, 3 },
	{ 0x298, 15, 4 },
	{ 0x298, 15, 5 },
	{ 0x298, 15, 6 },
	{ 0x298, 15, 7 },

	/* rgb 3 */
	{ 0x298, 30, 0 },
	{ 0x298, 30, 1 },
	{ 0x298, 30, 2 },
	{ 0x298, 30, 3 },
	{ 0x298, 30, 4 },
	{ 0x298, 30, 5 },
	{ 0x298, 30, 6 },
	{ 0x298, 30, 7 },

	{ 0x298, 31, 0 },
	{ 0x298, 31, 1 },
	{ 0x298, 31, 2 },
	{ 0x298, 31, 3 },
	{ 0x298, 31, 4 },
	{ 0x298, 31, 5 },
	{ 0x298, 31, 6 },
	{ 0x298, 31, 7 },

	{ 0x298, 32, 0 },
	{ 0x298, 32, 1 },
	{ 0x298, 32, 2 },
	{ 0x298, 32, 3 },
	{ 0x298, 32, 4 },
	{ 0x298, 32, 5 },
	{ 0x298, 32, 6 },
	{ 0x298, 32, 7 },

	{ 0x298, 34, 0 },
	{ 0x298, 34, 1 },
	{ 0x298, 34, 2 },
	{ 0x298, 34, 3 },
	{ 0x298, 34, 4 },
	{ 0x298, 34, 5 },
	{ 0x298, 34, 6 },
	{ 0x298, 34, 7 },

	{ 0x298, 35, 0 },
	{ 0x298, 35, 1 },
	{ 0x298, 35, 2 },
	{ 0x298, 35, 3 },
	{ 0x298, 35, 4 },
	{ 0x298, 35, 5 },
	{ 0x298, 35, 6 },
	{ 0x298, 35, 7 },

	/* dma 1 */
	{ 0x298, 40, 0 },
	{ 0x298, 40, 1 },
	{ 0x298, 40, 2 },
	{ 0x298, 40, 3 },
	{ 0x298, 40, 4 },
	{ 0x298, 40, 5 },
	{ 0x298, 40, 6 },
	{ 0x298, 40, 7 },

	{ 0x298, 41, 0 },
	{ 0x298, 41, 1 },
	{ 0x298, 41, 2 },
	{ 0x298, 41, 3 },
	{ 0x298, 41, 4 },
	{ 0x298, 41, 5 },
	{ 0x298, 41, 6 },
	{ 0x298, 41, 7 },

	{ 0x298, 42, 0 },
	{ 0x298, 42, 1 },
	{ 0x298, 42, 2 },
	{ 0x298, 42, 3 },
	{ 0x298, 42, 4 },
	{ 0x298, 42, 5 },
	{ 0x298, 42, 6 },
	{ 0x298, 42, 7 },

	{ 0x298, 44, 0 },
	{ 0x298, 44, 1 },
	{ 0x298, 44, 2 },
	{ 0x298, 44, 3 },
	{ 0x298, 44, 4 },
	{ 0x298, 44, 5 },
	{ 0x298, 44, 6 },
	{ 0x298, 44, 7 },

	{ 0x298, 45, 0 },
	{ 0x298, 45, 1 },
	{ 0x298, 45, 2 },
	{ 0x298, 45, 3 },
	{ 0x298, 45, 4 },
	{ 0x298, 45, 5 },
	{ 0x298, 45, 6 },
	{ 0x298, 45, 7 },

	/* cursor 1 */
	{ 0x298, 80, 0 },
	{ 0x298, 80, 1 },
	{ 0x298, 80, 2 },
	{ 0x298, 80, 3 },
	{ 0x298, 80, 4 },
	{ 0x298, 80, 5 },
	{ 0x298, 80, 6 },
	{ 0x298, 80, 7 },

	{ 0x298, 81, 0 },
	{ 0x298, 81, 1 },
	{ 0x298, 81, 2 },
	{ 0x298, 81, 3 },
	{ 0x298, 81, 4 },
	{ 0x298, 81, 5 },
	{ 0x298, 81, 6 },
	{ 0x298, 81, 7 },

	{ 0x298, 82, 0 },
	{ 0x298, 82, 1 },
	{ 0x298, 82, 2 },
	{ 0x298, 82, 3 },
	{ 0x298, 82, 4 },
	{ 0x298, 82, 5 },
	{ 0x298, 82, 6 },
	{ 0x298, 82, 7 },

	{ 0x298, 83, 0 },
	{ 0x298, 83, 1 },
	{ 0x298, 83, 2 },
	{ 0x298, 83, 3 },
	{ 0x298, 83, 4 },
	{ 0x298, 83, 5 },
	{ 0x298, 83, 6 },
	{ 0x298, 83, 7 },

	{ 0x298, 84, 0 },
	{ 0x298, 84, 1 },
	{ 0x298, 84, 2 },
	{ 0x298, 84, 3 },
	{ 0x298, 84, 4 },
	{ 0x298, 84, 5 },
	{ 0x298, 84, 6 },
	{ 0x298, 84, 7 },
};

static struct debug_bus dbg_bus_8994[] = {
	/* VIG QSEED */
	{ 0x298, 4, 0},
@@ -123,6 +703,18 @@ static struct debug_bus dbg_bus_8994[] = {
	{ 0x348, 43, 0},
};

static struct vbif_debug_bus vbif_dbg_bus_8996[] = {
	{0x214, 0x21c, 16, 2, 16}, /* arb clients */
	{0x214, 0x21c, 0, 14, 4}, /* xin blocks - axi side */
	{0x21c, 0x214, 0, 14, 5}, /* xin blocks - clock side */
};

static struct vbif_debug_bus nrt_vbif_dbg_bus_8996[] = {
	{0x214, 0x21c, 16, 1, 16}, /* arb clients */
	{0x214, 0x21c, 0, 12, 4}, /* xin blocks - axi side */
	{0x21c, 0x214, 0, 12, 5}, /* xin blocks - clock side */
};

void mdss_mdp_hw_rev_debug_caps_init(struct mdss_data_type *mdata)
{
	mdata->dbg_bus = NULL;
@@ -134,6 +726,17 @@ void mdss_mdp_hw_rev_debug_caps_init(struct mdss_data_type *mdata)
		mdata->dbg_bus = dbg_bus_8994;
		mdata->dbg_bus_size = ARRAY_SIZE(dbg_bus_8994);
		break;
	case MDSS_MDP_HW_REV_107:
	case MDSS_MDP_HW_REV_107_1:
	case MDSS_MDP_HW_REV_107_2:
		mdata->dbg_bus = dbg_bus_8996;
		mdata->dbg_bus_size = ARRAY_SIZE(dbg_bus_8996);
		mdata->vbif_dbg_bus = vbif_dbg_bus_8996;
		mdata->vbif_dbg_bus_size = ARRAY_SIZE(vbif_dbg_bus_8996);
		mdata->nrt_vbif_dbg_bus = nrt_vbif_dbg_bus_8996;
		mdata->nrt_vbif_dbg_bus_size =
			ARRAY_SIZE(nrt_vbif_dbg_bus_8996);
		break;
	default:
		break;
	}
+3 −0
Original line number Diff line number Diff line
@@ -674,6 +674,7 @@ enum mdss_mdp_pingpong_index {
/* Following offsets are with respect to MDP base */
#define MDSS_MDP_MDP_OUT_CTL_0                          0x410
/* following offsets are with respect to MDP VBIF base */
#define MMSS_VBIF_CLKON			0x4
#define MMSS_VBIF_RD_LIM_CONF			0x0B0
#define MMSS_VBIF_WR_LIM_CONF			0x0C0

@@ -681,6 +682,8 @@ enum mdss_mdp_pingpong_index {
#define MMSS_VBIF_XIN_HALT_CTRL1	0x204
#define MMSS_VBIF_AXI_HALT_CTRL0	0x208
#define MMSS_VBIF_AXI_HALT_CTRL1	0x20C
#define MMSS_VBIF_TEST_BUS_OUT_CTRL	0x210
#define MMSS_VBIF_TEST_BUS_OUT		0x230

#define MDSS_VBIF_QOS_REMAP_BASE	0x020
#define MDSS_VBIF_QOS_REMAP_ENTRIES	0x4