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Commit 978e8a2a authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Invoke DCVS callbacks on A540"

parents 7e970301 3dc90c51

drivers/gpu/msm/adreno.c

+2 −2
Original line number Diff line number Diff line
@@ -1223,7 +1223,7 @@ static void _setup_throttling_counters(struct adreno_device *adreno_dev) 
	if (!adreno_is_a540(adreno_dev))

		return;



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM))

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))

		return;



	for (i = 0; i < ADRENO_GPMU_THROTTLE_COUNTERS; i++) {
@@ -1261,7 +1261,7 @@ static uint64_t _read_throttling_counters(struct adreno_device *adreno_dev) 
	if (!adreno_is_a540(adreno_dev))

		return 0;



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM))

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))

		return 0;



	for (i = 0; i < ADRENO_GPMU_THROTTLE_COUNTERS; i++) {

drivers/gpu/msm/adreno_a5xx.c

+16 −4
Original line number Diff line number Diff line
@@ -1845,7 +1845,7 @@ static void a540_lm_init(struct adreno_device *adreno_dev) 
{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	uint32_t agc_lm_config =

		((ADRENO_CHIPID_PATCH(adreno_dev->chipid) | 0x3)

		((ADRENO_CHIPID_PATCH(adreno_dev->chipid) & 0x3)

		<< AGC_GPU_VERSION_SHIFT);

	unsigned int r, i;
@@ -1855,8 +1855,8 @@ static void a540_lm_init(struct adreno_device *adreno_dev) 
			AGC_THROTTLE_SEL_DCS;



		kgsl_regread(device, A5XX_GPMU_TEMP_SENSOR_CONFIG, &r);

		if (r & GPMU_BCL_ENABLED)

			agc_lm_config |= AGC_BCL_ENABLED;

		if (!(r & GPMU_BCL_ENABLED))

			agc_lm_config |= AGC_BCL_DISABLED;



		if (r & GPMU_LLM_ENABLED)

			agc_lm_config |= AGC_LLM_ENABLED;
@@ -1905,6 +1905,9 @@ start_agc: 
	kgsl_regwrite(device, A5XX_GPMU_GPMU_PWR_THRESHOLD,

		PWR_THRESHOLD_VALID | lm_limit(adreno_dev));



	kgsl_regwrite(device, A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK,

		VOLTAGE_INTR_EN);



	if (lm_on(adreno_dev))

		wake_llm(adreno_dev);

}
@@ -1953,7 +1956,10 @@ static void a5xx_pwrlevel_change_settings(struct adreno_device *adreno_dev, 
{

	int on = 0;



	/* Only call through if PPD or LM is supported and enabled */

	/*

	 * On pre A540 HW only call through if PPD or LMx

	 * is supported and enabled

	 */

	if (ADRENO_FEATURE(adreno_dev, ADRENO_PPD) &&

		test_bit(ADRENO_PPD_CTRL, &adreno_dev->pwrctrl_flag))

		on = ADRENO_PPD;
@@ -1962,6 +1968,12 @@ static void a5xx_pwrlevel_change_settings(struct adreno_device *adreno_dev, 
		test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))

		on = ADRENO_LM;



	/* On 540+ HW call through unconditionally as long as GPMU is enabled */

	if (ADRENO_FEATURE(adreno_dev, ADRENO_GPMU)) {

		if (adreno_is_a540(adreno_dev))

			on = ADRENO_GPMU;

	}



	if (!on)

		return;

drivers/gpu/msm/adreno_a5xx.h

+4 −1
Original line number Diff line number Diff line
@@ -167,6 +167,9 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on); 
#define AMP_CALIBRATION_RETRY_CNT	3

#define AMP_CALIBRATION_TIMEOUT		6



/* A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK */

#define VOLTAGE_INTR_EN			BIT(0)



/* A5XX_GPMU_GPMU_PWR_THRESHOLD */

#define PWR_THRESHOLD_VALID		0x80000000

/* AGC */
@@ -192,7 +195,7 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on); 
#define AGC_LLM_ENABLED			(1 << 16)

#define	AGC_GPU_VERSION_MASK		GENMASK(18, 17)

#define AGC_GPU_VERSION_SHIFT		17

#define AGC_BCL_ENABLED			(1 << 24)

#define AGC_BCL_DISABLED		(1 << 24)





#define AGC_LEVEL_CONFIG		(140/4)