[Blackfin] arch: Fix bug to Enable bf548 to Re-program Clocks while Kernel boots. (971d5bc4) · Commits · e / devices / android_kernel_xiaomi_markw

arch/blackfin/Kconfig

+17 −2

Original line number	Original line	Diff line number	Diff line
	@@ -317,7 +317,7 @@ config VCO_MULT
	range 1 64		range 1 64
	default "22" if BFIN533_EZKIT		default "22" if BFIN533_EZKIT
	default "45" if BFIN533_STAMP		default "45" if BFIN533_STAMP
	default "20" if (BFIN537_STAMP \|\| BFIN527_EZKIT)		default "20" if (BFIN537_STAMP \|\| BFIN527_EZKIT \|\| BFIN548_EZKIT)
	default "22" if BFIN533_BLUETECHNIX_CM		default "22" if BFIN533_BLUETECHNIX_CM
	default "20" if BFIN537_BLUETECHNIX_CM		default "20" if BFIN537_BLUETECHNIX_CM
	default "20" if BFIN561_BLUETECHNIX_CM		default "20" if BFIN561_BLUETECHNIX_CM
	@@ -354,7 +354,7 @@ config SCLK_DIV
	range 1 15		range 1 15
	default 5 if BFIN533_EZKIT		default 5 if BFIN533_EZKIT
	default 5 if BFIN533_STAMP		default 5 if BFIN533_STAMP
	default 4 if (BFIN537_STAMP \|\| BFIN527_EZKIT)		default 4 if (BFIN537_STAMP \|\| BFIN527_EZKIT \|\| BFIN548_EZKIT)
	default 5 if BFIN533_BLUETECHNIX_CM		default 5 if BFIN533_BLUETECHNIX_CM
	default 4 if BFIN537_BLUETECHNIX_CM		default 4 if BFIN537_BLUETECHNIX_CM
	default 4 if BFIN561_BLUETECHNIX_CM		default 4 if BFIN561_BLUETECHNIX_CM
	@@ -409,6 +409,7 @@ config MEM_SIZE
	default 32 if BFIN533_EZKIT		default 32 if BFIN533_EZKIT
	default 64 if BFIN527_EZKIT		default 64 if BFIN527_EZKIT
	default 64 if BFIN537_STAMP		default 64 if BFIN537_STAMP
			default 64 if BFIN548_EZKIT
	default 64 if BFIN561_EZKIT		default 64 if BFIN561_EZKIT
	default 128 if BFIN533_STAMP		default 128 if BFIN533_STAMP
	default 64 if PNAV10		default 64 if PNAV10
	@@ -416,6 +417,7 @@ config MEM_SIZE

	config MEM_ADD_WIDTH		config MEM_ADD_WIDTH
	int "SDRAM Memory Address Width"		int "SDRAM Memory Address Width"
			depends on (!BF54x)
	default 9 if BFIN533_EZKIT		default 9 if BFIN533_EZKIT
	default 9 if BFIN561_EZKIT		default 9 if BFIN561_EZKIT
	default 9 if H8606_HVSISTEMAS		default 9 if H8606_HVSISTEMAS
	@@ -424,6 +426,19 @@ config MEM_ADD_WIDTH
	default 11 if BFIN533_STAMP		default 11 if BFIN533_STAMP
	default 10 if PNAV10		default 10 if PNAV10


			choice
			prompt "DDR SDRAM Chip Type"
			depends on BFIN548_EZKIT
			default MEM_MT46V32M16_5B

			config MEM_MT46V32M16_6T
			bool "MT46V32M16_6T"

			config MEM_MT46V32M16_5B
			bool "MT46V32M16_5B"
			endchoice

	config ENET_FLASH_PIN		config ENET_FLASH_PIN
	int "PF port/pin used for flash and ethernet sharing"		int "PF port/pin used for flash and ethernet sharing"
	depends on (BFIN533_STAMP)		depends on (BFIN533_STAMP)

arch/blackfin/mach-bf548/head.S

+47 −0

Original line number	Original line	Diff line number	Diff line
	@@ -324,12 +324,25 @@ ENTRY(_start_dma_code)
	w[p0] = r0.l;		w[p0] = r0.l;
	ssync;		ssync;

			#if defined(CONFIG_BF54x)
			P2.H = hi(EBIU_RSTCTL);
			P2.L = lo(EBIU_RSTCTL);
			R0 = [P2];
			BITSET (R0, 3);
			#else
	P2.H = hi(EBIU_SDGCTL);		P2.H = hi(EBIU_SDGCTL);
	P2.L = lo(EBIU_SDGCTL);		P2.L = lo(EBIU_SDGCTL);
	R0 = [P2];		R0 = [P2];
	BITSET (R0, 24);		BITSET (R0, 24);
			#endif
	[P2] = R0;		[P2] = R0;
	SSYNC;		SSYNC;
			#if defined(CONFIG_BF54x)
			.LSRR_MODE:
			R0 = [P2];
			CC = BITTST(R0, 4);
			if !CC JUMP .LSRR_MODE;
			#endif

	r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */		r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
	r0 = r0 << 9; /* Shift it over, */		r0 = r0 << 9; /* Shift it over, */
	@@ -361,6 +374,39 @@ ENTRY(_start_dma_code)
	w[p0] = r0.l;		w[p0] = r0.l;
	ssync;		ssync;

			#if defined(CONFIG_BF54x)
			P2.H = hi(EBIU_RSTCTL);
			P2.L = lo(EBIU_RSTCTL);
			R0 = [P2];
			CC = BITTST(R0, 0);
			if CC jump .Lskipddrrst;
			BITSET (R0, 0);
			.Lskipddrrst:
			BITCLR (R0, 3);
			[P2] = R0;
			SSYNC;

			p0.l = lo(EBIU_DDRCTL0);
			p0.h = hi(EBIU_DDRCTL0);
			r0.l = lo(mem_DDRCTL0);
			r0.h = hi(mem_DDRCTL0);
			[p0] = r0;
			ssync;

			p0.l = lo(EBIU_DDRCTL1);
			p0.h = hi(EBIU_DDRCTL1);
			r0.l = lo(mem_DDRCTL1);
			r0.h = hi(mem_DDRCTL1);
			[p0] = r0;
			ssync;

			p0.l = lo(EBIU_DDRCTL2);
			p0.h = hi(EBIU_DDRCTL2);
			r0.l = lo(mem_DDRCTL2);
			r0.h = hi(mem_DDRCTL2);
			[p0] = r0;
			ssync;
			#else
	p0.l = lo(EBIU_SDRRC);		p0.l = lo(EBIU_SDRRC);
	p0.h = hi(EBIU_SDRRC);		p0.h = hi(EBIU_SDRRC);
	r0 = mem_SDRRC;		r0 = mem_SDRRC;
	@@ -394,6 +440,7 @@ ENTRY(_start_dma_code)
	R1 = R1 \| R0;		R1 = R1 \| R0;
	[P2] = R1;		[P2] = R1;
	SSYNC;		SSYNC;
			#endif

	p0.h = hi(SIC_IWR0);		p0.h = hi(SIC_IWR0);
	p0.l = lo(SIC_IWR0);		p0.l = lo(SIC_IWR0);

include/asm-blackfin/mach-bf548/defBF54x_base.h

+29 −2

Original line number	Original line	Diff line number	Diff line
	@@ -1772,17 +1772,36 @@
	#define TRP 0x3c0000 /* Pre charge-to-active command period */		#define TRP 0x3c0000 /* Pre charge-to-active command period */
	#define TRAS 0x3c00000 /* Min Active-to-pre charge time */		#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
	#define TRC 0x3c000000 /* Active-to-active time */		#define TRC 0x3c000000 /* Active-to-active time */
			#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
			#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
			#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
			#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
			#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */

	/* Bit masks for EBIU_DDRCTL1 */		/* Bit masks for EBIU_DDRCTL1 */

	#define TRCD 0xf /* Active-to-Read/write delay */		#define TRCD 0xf /* Active-to-Read/write delay */
	#define MRD 0xf0 /* Mode register set to active */		#define TMRD 0xf0 /* Mode register set to active */
	#define TWR 0x300 /* Write Recovery time */		#define TWR 0x300 /* Write Recovery time */
	#define DDRDATWIDTH 0x3000 /* DDR data width */		#define DDRDATWIDTH 0x3000 /* DDR data width */
	#define EXTBANKS 0xc000 /* External banks */		#define EXTBANKS 0xc000 /* External banks */
	#define DDRDEVWIDTH 0x30000 /* DDR device width */		#define DDRDEVWIDTH 0x30000 /* DDR device width */
	#define DDRDEVSIZE 0xc0000 /* DDR device size */		#define DDRDEVSIZE 0xc0000 /* DDR device size */
	#define TWWTR 0xf0000000 /* Write-to-read delay */		#define TWTR 0xf0000000 /* Write-to-read delay */
			#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
			#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
			#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
			#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
			#define DDR_DATWIDTH 0x2000 /* DDR data width */
			#define EXTBANK_1 0 /* 1 external bank */
			#define EXTBANK_2 0x4000 /* 2 external banks */
			#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
			#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
			#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
			#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
			#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
			#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
			#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */

	/* Bit masks for EBIU_DDRCTL2 */		/* Bit masks for EBIU_DDRCTL2 */

	@@ -1790,6 +1809,10 @@
	#define CASLATENCY 0x70 /* CAS latency */		#define CASLATENCY 0x70 /* CAS latency */
	#define DLLRESET 0x100 /* DLL Reset */		#define DLLRESET 0x100 /* DLL Reset */
	#define REGE 0x1000 /* Register mode enable */		#define REGE 0x1000 /* Register mode enable */
			#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
			#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
			#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
			#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */

	/* Bit masks for EBIU_DDRCTL3 */		/* Bit masks for EBIU_DDRCTL3 */

	@@ -2257,6 +2280,10 @@

	#define CSEL 0x30 /* Core Select */		#define CSEL 0x30 /* Core Select */
	#define SSEL 0xf /* System Select */		#define SSEL 0xf /* System Select */
			#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
			#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
			#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
			#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */

	/* Bit masks for PLL_CTL */		/* Bit masks for PLL_CTL */

include/asm-blackfin/mach-bf548/mem_init.h

+60 −1

Original line number	Original line	Diff line number	Diff line
	@@ -28,10 +28,69 @@
	* If not, write to the Free Software Foundation,		* If not, write to the Free Software Foundation,
	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.		* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	*/		*/
			#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)

	#if (CONFIG_MEM_MT46V32M16)		#if (CONFIG_MEM_MT46V32M16_6T)
			#define DDR_SIZE DEVSZ_512
			#define DDR_WIDTH DEVWD_16

			#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
			#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
			#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
			#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
			#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))

			#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
			#define DDR_tWTR DDR_TWTR(1)
			#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
			#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
			#endif

			#if (CONFIG_MEM_MT46V32M16_5B)
			#define DDR_SIZE DEVSZ_512
			#define DDR_WIDTH DEVWD_16

			#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
			#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
			#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
			#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
			#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))

			#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
			#define DDR_tWTR DDR_TWTR(2)
			#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
			#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
			#endif

			#if (CONFIG_MEM_GENERIC_BOARD)
			#define DDR_SIZE DEVSZ_512
			#define DDR_WIDTH DEVWD_16

			#define DDR_tRCD DDR_TRCD(3)
			#define DDR_tWTR DDR_TWTR(2)
			#define DDR_tWR DDR_TWR(2)
			#define DDR_tMRD DDR_TMRD(2)
			#define DDR_tRP DDR_TRP(3)
			#define DDR_tRAS DDR_TRAS(7)
			#define DDR_tRC DDR_TRC(10)
			#define DDR_tRFC DDR_TRFC(12)
			#define DDR_tREFI DDR_TREFI(1288)
	#endif		#endif

			#if (CONFIG_SCLK_HZ <= 133333333)
			#define DDR_CL CL_2
			#elif (CONFIG_SCLK_HZ <= 166666666)
			#define DDR_CL CL_2_5
			#else
			#define DDR_CL CL_3
			#endif

			#define mem_DDRCTL0 (DDR_tRP \| DDR_tRAS \| DDR_tRC \| DDR_tRFC \| DDR_tREFI)
			#define mem_DDRCTL1 (DDR_DATWIDTH \| EXTBANK_1 \| DDR_SIZE \| DDR_WIDTH \| DDR_tWTR \
			\| DDR_tMRD \| DDR_tWR \| DDR_tRCD)
			#define mem_DDRCTL2 DDR_CL


	#if defined CONFIG_CLKIN_HALF		#if defined CONFIG_CLKIN_HALF
	#define CLKIN_HALF 1		#define CLKIN_HALF 1
	#else		#else