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Commit 970eaff1 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: clock-cpu-8939: Re-org cpu clock code for spm pll management"

parents 4551e1ce 8793c290

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ Required properties: 
			"qcom,gcc-8994"

			"qcom,gcc-8994v2"

			"qcom,gcc-8952"

			"qcom,gcc-spm-8952"

			"qcom,gcc-fsm9010"

			"qcom,gcc-8996"

			"qcom,gcc-8996-v2"

arch/arm/boot/dts/qcom/msm8952.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ 
	cci_cache: qcom,cci {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_cpu clk_a53ssmux_cci>;

		clocks = <&clock_cpu clk_cci_clk>;

		governor = "cpufreq";

		freq-tbl-khz =

			<  200000 >,
@@ -304,15 +304,15 @@ 
		clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",

				"cpu3_clk", "cpu4_clk", "cpu5_clk",

				"cpu6_clk", "cpu7_clk";

		clocks = <&clock_cpu clk_a53ssmux_cci>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_bc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>;

		clocks = <&clock_cpu clk_cci_clk>,

			 <&clock_cpu clk_a53_bc_clk>,

			 <&clock_cpu clk_a53_bc_clk>,

			 <&clock_cpu clk_a53_bc_clk>,

			 <&clock_cpu clk_a53_bc_clk>,

			 <&clock_cpu clk_a53_lc_clk>,

			 <&clock_cpu clk_a53_lc_clk>,

			 <&clock_cpu clk_a53_lc_clk>,

			 <&clock_cpu clk_a53_lc_clk>;



		qcom,governor-per-policy;

drivers/clk/msm/clock-cpu-8939.c

+150 −37
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <linux/mutex.h>

#include <linux/delay.h>

#include <linux/platform_device.h>

#include <linux/pm_qos.h>

#include <linux/regulator/consumer.h>

#include <linux/of.h>

#include <linux/clk/msm-clock-generic.h>
@@ -46,6 +47,14 @@ enum { 


const char *mux_names[] = { "c1", "c0", "cci"};



struct cpu_clk_8939 {

	u32 cpu_reg_mask;

	cpumask_t cpumask;

	bool hw_low_power_ctrl;

	struct pm_qos_request req;

	struct clk c;

};



static struct mux_div_clk a53ssmux_bc = {

	.ops = &rcg_mux_div_ops,

	.safe_freq = 400000000,
@@ -57,7 +66,6 @@ static struct mux_div_clk a53ssmux_bc = { 
	.c = {

		.dbg_name = "a53ssmux_bc",

		.ops = &clk_ops_mux_div_clk,

		.vdd_class = &vdd_cpu_bc,

		CLK_INIT(a53ssmux_bc.c),

	},

	.parents = (struct clk_src[8]) {},
@@ -77,7 +85,6 @@ static struct mux_div_clk a53ssmux_lc = { 
	.c = {

		.dbg_name = "a53ssmux_lc",

		.ops = &clk_ops_mux_div_clk,

		.vdd_class = &vdd_cpu_lc,

		CLK_INIT(a53ssmux_lc.c),

	},

	.parents = (struct clk_src[8]) {},
@@ -97,7 +104,6 @@ static struct mux_div_clk a53ssmux_cci = { 
	.c = {

		.dbg_name = "a53ssmux_cci",

		.ops = &clk_ops_mux_div_clk,

		.vdd_class = &vdd_cpu_cci,

		CLK_INIT(a53ssmux_cci.c),

	},

	.parents = (struct clk_src[8]) {},
@@ -106,15 +112,120 @@ static struct mux_div_clk a53ssmux_cci = { 
	.src_shift = 8,

};



static void do_nothing(void *unused) { }

#define CPU_LATENCY_NO_L2_PC_US (300)



static inline struct cpu_clk_8939 *to_cpu_clk_8939(struct clk *c)

{

	return container_of(c, struct cpu_clk_8939, c);

}



static enum handoff cpu_clk_8939_handoff(struct clk *c)

{

	c->rate = clk_get_rate(c->parent);

	return HANDOFF_DISABLED_CLK;

}



static long cpu_clk_8939_round_rate(struct clk *c, unsigned long rate)

{

	return clk_round_rate(c->parent, rate);

}



static int cpu_clk_8939_set_rate(struct clk *c, unsigned long rate)

{

	int ret = 0;

	struct cpu_clk_8939 *cpuclk = to_cpu_clk_8939(c);

	bool hw_low_power_ctrl = cpuclk->hw_low_power_ctrl;



	if (hw_low_power_ctrl) {

		memset(&cpuclk->req, 0, sizeof(cpuclk->req));

		cpumask_copy(&cpuclk->req.cpus_affine,

				(const struct cpumask *)&cpuclk->cpumask);

		cpuclk->req.type = PM_QOS_REQ_AFFINE_CORES;

		pm_qos_add_request(&cpuclk->req, PM_QOS_CPU_DMA_LATENCY,

				CPU_LATENCY_NO_L2_PC_US);

		smp_call_function_any(&cpuclk->cpumask, do_nothing,

				NULL, 1);

	}



	ret = clk_set_rate(c->parent, rate);



	if (hw_low_power_ctrl)

		pm_qos_remove_request(&cpuclk->req);



	return ret;

}



static struct clk_ops clk_ops_cpu = {

	.set_rate = cpu_clk_8939_set_rate,

	.round_rate = cpu_clk_8939_round_rate,

	.handoff = cpu_clk_8939_handoff,

};



static struct cpu_clk_8939 a53_bc_clk = {

	.cpu_reg_mask = 0x3,

	.c = {

		.parent = &a53ssmux_bc.c,

		.ops = &clk_ops_cpu,

		.vdd_class = &vdd_cpu_bc,

		.dbg_name = "a53_bc_clk",

		CLK_INIT(a53_bc_clk.c),

	},

};



static struct cpu_clk_8939 a53_lc_clk = {

	.cpu_reg_mask = 0x103,

	.c = {

		.parent = &a53ssmux_lc.c,

		.ops = &clk_ops_cpu,

		.vdd_class = &vdd_cpu_lc,

		.dbg_name = "a53_lc_clk",

		CLK_INIT(a53_lc_clk.c),

	},

};



static struct cpu_clk_8939 cci_clk = {

	.c = {

		.parent = &a53ssmux_cci.c,

		.ops = &clk_ops_cpu,

		.vdd_class = &vdd_cpu_cci,

		.dbg_name = "cci_clk",

		CLK_INIT(cci_clk.c),

	},

};



static struct clk_lookup cpu_clocks_8939[] = {

	CLK_LIST(a53ssmux_lc),

	CLK_LIST(a53ssmux_bc),

	CLK_LIST(a53ssmux_cci),

	CLK_LIST(a53_bc_clk),

	CLK_LIST(a53_lc_clk),

	CLK_LIST(cci_clk),

};



static struct mux_div_clk *a53ssmux[] = {&a53ssmux_bc,

						&a53ssmux_lc, &a53ssmux_cci};



static struct cpu_clk_8939 *cpuclk[] = { &a53_bc_clk, &a53_lc_clk, &cci_clk};



static struct clk *logical_cpu_to_clk(int cpu)

{

	struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);

	u32 reg;



	/* CPU 0/1/2/3 --> a53_bc_clk and mask = 0x103

	 * CPU 4/5/6/7 --> a53_lc_clk and mask = 0x3

	 */

	if (cpu_node && !of_property_read_u32(cpu_node, "reg", &reg)) {

		if ((reg | a53_bc_clk.cpu_reg_mask) == a53_bc_clk.cpu_reg_mask)

			return &a53_lc_clk.c;

		if ((reg | a53_lc_clk.cpu_reg_mask) == a53_lc_clk.cpu_reg_mask)

			return &a53_bc_clk.c;

	}



	return NULL;

}



static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c,

								char *prop_name)

{
@@ -306,7 +417,7 @@ static int cpu_parse_devicetree(struct platform_device *pdev, int mux_id) 
			dev_err(&pdev->dev, "unable to get regulator\n");

		return PTR_ERR(regulator);

	}

	a53ssmux[mux_id]->c.vdd_class->regulator[0] = regulator;

	cpuclk[mux_id]->c.vdd_class->regulator[0] = regulator;



	rc = of_get_clk_src(pdev, a53ssmux[mux_id]->parents, mux_id);

	if (IS_ERR_VALUE(rc))
@@ -410,10 +521,10 @@ static void print_opp_table(int a53_c0_cpu, int a53_c1_cpu) 
	struct dev_pm_opp *oppfmax, *oppfmin;

	unsigned long apc0_fmax, apc1_fmax, apc0_fmin, apc1_fmin;



	apc0_fmax = a53ssmux_lc.c.fmax[a53ssmux_lc.c.num_fmax - 1];

	apc1_fmax = a53ssmux_bc.c.fmax[a53ssmux_bc.c.num_fmax - 1];

	apc0_fmin = a53ssmux_lc.c.fmax[1];

	apc1_fmin = a53ssmux_bc.c.fmax[1];

	apc0_fmax = a53_lc_clk.c.fmax[a53_lc_clk.c.num_fmax - 1];

	apc1_fmax = a53_bc_clk.c.fmax[a53_bc_clk.c.num_fmax - 1];

	apc0_fmin = a53_lc_clk.c.fmax[1];

	apc1_fmin = a53_bc_clk.c.fmax[1];



	rcu_read_lock();

	oppfmax = dev_pm_opp_find_freq_exact(get_cpu_device(a53_c0_cpu),
@@ -469,19 +580,19 @@ static void populate_opp_table(struct platform_device *pdev) 
		return;

	}



	apc0_fmax = a53ssmux_lc.c.fmax[a53ssmux_lc.c.num_fmax - 1];

	apc1_fmax = a53ssmux_bc.c.fmax[a53ssmux_bc.c.num_fmax - 1];

	apc0_fmax = a53_lc_clk.c.fmax[a53_lc_clk.c.num_fmax - 1];

	apc1_fmax = a53_bc_clk.c.fmax[a53_bc_clk.c.num_fmax - 1];



	for_each_possible_cpu(cpu) {

		pr_info("the CPU number is : %d\n", cpu);

		pr_debug("the CPU number is : %d\n", cpu);

		if (cpu/4 == 0) {

			a53_c1_cpu = cpu;

			WARN(add_opp(&a53ssmux_bc.c, get_cpu_device(cpu),

			WARN(add_opp(&a53_bc_clk.c, get_cpu_device(cpu),

				     &apc1_dev->dev, apc1_fmax),

				     "Failed to add OPP levels for A53 big cluster\n");

		} else if (cpu/4 == 1) {

			a53_c0_cpu = cpu;

			WARN(add_opp(&a53ssmux_lc.c, get_cpu_device(cpu),

			WARN(add_opp(&a53_lc_clk.c, get_cpu_device(cpu),

				     &apc0_dev->dev, apc0_fmax),

				     "Failed to add OPP levels for A53 little cluster\n");

		}
@@ -517,15 +628,15 @@ static int clock_8939_pm_event(struct notifier_block *this, 
	switch (event) {

	case PM_POST_HIBERNATION:

	case PM_POST_SUSPEND:

		clk_unprepare(&a53ssmux_lc.c);

		clk_unprepare(&a53ssmux_bc.c);

		clk_unprepare(&a53ssmux_cci.c);

		clk_unprepare(&a53_lc_clk.c);

		clk_unprepare(&a53_bc_clk.c);

		clk_unprepare(&cci_clk.c);

		break;

	case PM_HIBERNATION_PREPARE:

	case PM_SUSPEND_PREPARE:

		clk_prepare(&a53ssmux_lc.c);

		clk_prepare(&a53ssmux_bc.c);

		clk_prepare(&a53ssmux_cci.c);

		clk_prepare(&a53_lc_clk.c);

		clk_prepare(&a53_bc_clk.c);

		clk_prepare(&cci_clk.c);

		break;

	default:

		break;
@@ -537,8 +648,6 @@ static struct notifier_block clock_8939_pm_notifier = { 
	.notifier_call = clock_8939_pm_event,

};



struct platform_device *cpu_clock_8939_dev;



static int clock_a53_probe(struct platform_device *pdev)

{

	int speed_bin, version, rc, cpu, mux_id, rate;
@@ -555,7 +664,7 @@ static int clock_a53_probe(struct platform_device *pdev) 
					"qcom,speed%d-bin-v%d-%s",

					speed_bin, version, mux_names[mux_id]);



		rc = of_get_fmax_vdd_class(pdev, &a53ssmux[mux_id]->c,

		rc = of_get_fmax_vdd_class(pdev, &cpuclk[mux_id]->c,

								prop_name);

		if (rc) {

			/* Fall back to most conservative PVS table */
@@ -564,7 +673,7 @@ static int clock_a53_probe(struct platform_device *pdev) 


			snprintf(prop_name, ARRAY_SIZE(prop_name),

				"qcom,speed0-bin-v0-%s", mux_names[mux_id]);

			rc = of_get_fmax_vdd_class(pdev, &a53ssmux[mux_id]->c,

			rc = of_get_fmax_vdd_class(pdev, &cpuclk[mux_id]->c,

								prop_name);

			if (rc) {

				dev_err(&pdev->dev,
@@ -582,8 +691,8 @@ static int clock_a53_probe(struct platform_device *pdev) 
		return rc;

	}



	rate = clk_get_rate(&a53ssmux[A53SS_MUX_CCI]->c);

	clk_set_rate(&a53ssmux[A53SS_MUX_CCI]->c, rate);

	rate = clk_get_rate(&cci_clk.c);

	clk_set_rate(&cci_clk.c, rate);



	for (mux_id = 0; mux_id < A53SS_MUX_CCI; mux_id++) {

		/* Force a PLL reconfiguration */
@@ -599,13 +708,26 @@ static int clock_a53_probe(struct platform_device *pdev) 
	 */

	get_online_cpus();

	for_each_online_cpu(cpu) {

		WARN(clk_prepare_enable(&a53ssmux[cpu/4]->c),

		WARN(clk_prepare_enable(&cpuclk[cpu/4]->c),

				"Unable to turn on CPU clock");

		clk_prepare_enable(&a53ssmux_cci.c);

		clk_prepare_enable(&cci_clk.c);

	}

	put_online_cpus();



	for_each_possible_cpu(cpu) {

		if (logical_cpu_to_clk(cpu) == &a53_bc_clk.c)

			cpumask_set_cpu(cpu, &a53_bc_clk.cpumask);

		if (logical_cpu_to_clk(cpu) == &a53_lc_clk.c)

			cpumask_set_cpu(cpu, &a53_lc_clk.cpumask);

	}



	a53_lc_clk.hw_low_power_ctrl = true;

	a53_bc_clk.hw_low_power_ctrl = true;



	register_pm_notifier(&clock_8939_pm_notifier);

	cpu_clock_8939_dev = pdev;



	populate_opp_table(pdev);



	return 0;

}
@@ -629,15 +751,6 @@ static int __init clock_a53_init(void) 
}

arch_initcall(clock_a53_init);



/* CPU devices are not currently available in arch_initcall */

static int __init cpu_clock_8939_init_opp(void)

{

	if (cpu_clock_8939_dev)

		populate_opp_table(cpu_clock_8939_dev);

	return 0;

}

module_init(cpu_clock_8939_init_opp);



#define APCS_C0_PLL			0xb116000

#define C0_PLL_MODE			0x0

#define C0_PLL_L_VAL			0x4

drivers/clk/msm/clock-gcc-8952.c

+87 −1
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include <linux/platform_device.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_platform.h>

#include <soc/qcom/clock-local2.h>

#include <soc/qcom/clock-pll.h>

#include <soc/qcom/clock-alpha-pll.h>
@@ -265,6 +266,10 @@ static struct pll_clk a53ss_cci_pll = { 
		.main_output_mask = BIT(0),

	},

	.base = &virt_bases[APCS_CCI_PLL_BASE],

	.spm_ctrl = {

		.offset = 0x40,

		.event_bit = 0x0,

	},

	.c = {

		.parent = &xo_a_clk_src.c,

		.dbg_name = "a53ss_cci_pll",
@@ -311,6 +316,10 @@ static struct pll_clk a53ss_c0_pll = { 
		.main_output_mask = BIT(0),

	},

	.base = &virt_bases[APCS_C0_PLL_BASE],

	.spm_ctrl = {

		.offset = 0x50,

		.event_bit = 0x4,

	},

	.c = {

		.parent = &xo_a_clk_src.c,

		.dbg_name = "a53ss_c0_pll",
@@ -366,6 +375,10 @@ static struct pll_clk a53ss_c1_pll = { 
		.main_output_mask = BIT(0),

	},

	.base = &virt_bases[APCS_C1_PLL_BASE],

	.spm_ctrl = {

		.offset = 0x50,

		.event_bit = 0x4,

	},

	.c = {

		.parent = &xo_a_clk_src.c,

		.dbg_name = "a53ss_c1_pll",
@@ -3569,6 +3582,10 @@ static int msm_gcc_probe(struct platform_device *pdev) 
	regval |= CLKFLAG_SLEEP_CYCLES << 4;

	writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));



	ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);

	if (ret)

		return ret;



	dev_info(&pdev->dev, "Registered GCC clocks\n");



	return 0;
@@ -3588,9 +3605,78 @@ static struct platform_driver msm_clock_gcc_driver = { 
	},

};



static int msm_gcc_spm_probe(struct platform_device *pdev)

{

	struct resource *res = NULL;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c0_base");

	if (!res) {

		dev_err(&pdev->dev, "SPM register base not defined for c0\n");

		return -ENOMEM;

	}



	a53ss_c0_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,

						resource_size(res));

	if (!a53ss_c0_pll.spm_ctrl.spm_base) {

		dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");

		return -ENOMEM;

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c1_base");

	if (!res) {

		dev_err(&pdev->dev, "SPM register base not defined for c1\n");

		return -ENOMEM;

	}



	a53ss_c1_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,

						resource_size(res));

	if (!a53ss_c1_pll.spm_ctrl.spm_base) {

		dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");

		return -ENOMEM;

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

						"spm_cci_base");

	if (!res) {

		dev_err(&pdev->dev, "SPM register base not defined for cci\n");

		return -ENOMEM;

	}



	a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,

						resource_size(res));

	if (!a53ss_cci_pll.spm_ctrl.spm_base) {

		dev_err(&pdev->dev, "Failed to ioremap cci spm registers\n");

		return -ENOMEM;

	}



	dev_info(&pdev->dev, "Registered GCC SPM clocks\n");



	return 0;

}



static struct of_device_id msm_clock_spm_match_table[] = {

	{ .compatible = "qcom,gcc-spm-8952" },

	{}

};



static struct platform_driver msm_clock_spm_driver = {

	.probe = msm_gcc_spm_probe,

	.driver = {

		.name = "qcom,gcc-spm-8952",

		.of_match_table = msm_clock_spm_match_table,

		.owner = THIS_MODULE,

	},

};



static int __init msm_gcc_init(void)

{

	return platform_driver_register(&msm_clock_gcc_driver);

	int ret;



	ret = platform_driver_register(&msm_clock_gcc_driver);

	if (!ret)

		ret = platform_driver_register(&msm_clock_spm_driver);



	return ret;

}



static struct clk_lookup msm_clocks_measure[] = {

drivers/clk/msm/clock-pll.c

+55 −0
Original line number Diff line number Diff line
@@ -55,6 +55,8 @@ static DEFINE_SPINLOCK(pll_reg_lock); 
#define ENABLE_WAIT_MAX_LOOPS 200

#define PLL_LOCKED_BIT BIT(16)



#define SPM_FORCE_EVENT   0x4



static int pll_vote_clk_enable(struct clk *c)

{

	u32 ena, count;
@@ -137,6 +139,54 @@ struct clk_ops clk_ops_pll_vote = { 
	.list_registers = pll_vote_clk_list_registers,

};



/*

 *  spm_event() -- Set/Clear SPM events

 *  PLL off sequence -- enable (1)

 *    Set L2_SPM_FORCE_EVENT_EN[bit] register to 1

 *    Set L2_SPM_FORCE_EVENT[bit] register to 1

 *  PLL on sequence -- enable (0)

 *   Clear L2_SPM_FORCE_EVENT[bit] register to 0

 *   Clear L2_SPM_FORCE_EVENT_EN[bit] register to 0

 */

static void spm_event(void __iomem *base, u32 offset, u32 bit,

							bool enable)

{

	uint32_t val;



	if (!base)

		return;



	if (enable) {

		/* L2_SPM_FORCE_EVENT_EN */

		val = readl_relaxed(base + offset);

		val |= BIT(bit);

		writel_relaxed(val, (base + offset));

		/* Ensure that the write above goes through. */

		mb();



		/* L2_SPM_FORCE_EVENT */

		val = readl_relaxed(base + offset + SPM_FORCE_EVENT);

		val |= BIT(bit);

		writel_relaxed(val, (base + offset + SPM_FORCE_EVENT));

		/* Ensure that the write above goes through. */

		mb();

	} else {

		/* L2_SPM_FORCE_EVENT */

		val = readl_relaxed(base + offset + SPM_FORCE_EVENT);

		val &= ~BIT(bit);

		writel_relaxed(val, (base + offset + SPM_FORCE_EVENT));

		/* Ensure that the write above goes through. */

		mb();



		/* L2_SPM_FORCE_EVENT_EN */

		val = readl_relaxed(base + offset);

		val &= ~BIT(bit);

		writel_relaxed(val, (base + offset));

		/* Ensure that the write above goes through. */

		mb();

	}

}



static void __pll_config_reg(void __iomem *pll_config, struct pll_freq_tbl *f,

			struct pll_config_masks *masks)

{
@@ -175,6 +225,9 @@ static int sr2_pll_clk_enable(struct clk *c) 


	spin_lock_irqsave(&pll_reg_lock, flags);



	spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset,

				pll->spm_ctrl.event_bit, false);



	/* Disable PLL bypass mode. */

	mode |= PLL_BYPASSNL;

	writel_relaxed(mode, PLL_MODE_REG(pll));
@@ -528,6 +581,8 @@ static void local_pll_clk_disable(struct clk *c) 
	 * the bypass mode, and assert the reset.

	 */

	spin_lock_irqsave(&pll_reg_lock, flags);

	spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset,

				pll->spm_ctrl.event_bit, true);

	__pll_clk_disable_reg(PLL_MODE_REG(pll));

	spin_unlock_irqrestore(&pll_reg_lock, flags);

}