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Commit 96d37bfd authored by Alok Chauhan's avatar Alok Chauhan Committed by Sridhar Ancha
Browse files

msm: emac: Correct phy programming sequence on mdm9607 



correct sgmii phy sequence as per recommendation from hw
team.

CRs-fixed: 965249

Change-Id: I7bb21b484f7597c462b7076344b0fd960b0dc6e3
Signed-off-by: default avatarAlok Chauhan <alokc@codeaurora.org>
Signed-off-by: default avatarSridhar Ancha <sancha@codeaurora.org>
parent 184e2ced

drivers/net/ethernet/qualcomm/emac/emac_defines.h

+4 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.

*

* This program is free software; you can redistribute it and/or modify

* it under the terms of the GNU General Public License version 2 and
@@ -410,6 +410,9 @@ 
/* EMAC_QSERDES_COM_RESETSM_CNTRL */

#define FRQ_TUNE_MODE                                              0x10



/* EMAC_QSERDES_COM_RES_TRIM_SEARCH */

#define RESTRIM_SEARCH						   0x0



/* EMAC_QSERDES_COM_BGTC */

#define BGTC							   0x7

drivers/net/ethernet/qualcomm/emac/emac_sgmii.h

+6 −11
Original line number Diff line number Diff line 
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -86,18 +86,13 @@ 
#define QSERDES_RX_CDR_CTRL1_GAIN       0x02

#define QSERDES_RX_CDR_CTRL2_THRESH     0x03

#define QSERDES_RX_CDR_CTRL2_GAIN       0x04

#define QSERDES_RX_EQ_GAIN2_DEF              0xf

#define QSERDES_RX_EQ_GAIN1_DEF              0xf

#define QSERDES_RX_EQ_GAIN2_MDM              0x3

#define QSERDES_RX_EQ_GAIN1_MDM              0x3

#define QSERDES_RX_EQ_GAIN2             0xf

#define QSERDES_RX_EQ_GAIN1             0xf



#define QSERDES_TX_BIST_MODE_LANENO     0x00

#define QSERDES_TX_DRV_LVL_DEF              0x0f

#define QSERDES_TX_EMP_POST1_LVL_DEF           1

#define QSERDES_TX_LANE_MODE_DEF            0x08

#define QSERDES_TX_DRV_LVL_MDM              0x0c

#define QSERDES_TX_EMP_POST1_LVL_MDM           4

#define QSERDES_TX_LANE_MODE_MDM            0x00

#define QSERDES_TX_DRV_LVL              0x0f

#define QSERDES_TX_EMP_POST1_LVL           1

#define QSERDES_TX_LANE_MODE            0x08



#define SGMII_PHY_IRQ_CLR_WAIT_TIME     10

drivers/net/ethernet/qualcomm/emac/emac_sgmii_v1.c

+17 −41
Original line number Diff line number Diff line 
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -17,8 +17,7 @@ 
#include "emac_hw.h"



#define PCS_MAX_REG_CNT		10

#define PLL_MAX_REG_CNT		17

#define TX_RX_MAX_REG_CNT	7

#define PLL_MAX_REG_CNT		18



static const struct emac_reg_write

		physical_coding_sublayer_programming[][PCS_MAX_REG_CNT] = {
@@ -115,6 +114,7 @@ static const struct emac_reg_write pll_setting[][PLL_MAX_REG_CNT] = { 
		{EMAC_QSERDES_COM_PLLLOCK_CMP3,		QSERDES_PLL_LOCK_CMP3},

		{EMAC_QSERDES_COM_PLLLOCK_CMP_EN,	PLLLOCK_CMP_EN},

		{EMAC_QSERDES_COM_RESETSM_CNTRL,	FRQ_TUNE_MODE},

		{EMAC_QSERDES_COM_RES_TRIM_SEARCH,	RESTRIM_SEARCH},

		{EMAC_QSERDES_COM_BGTC,				BGTC},

		{END_MARKER,				END_MARKER},

	}
@@ -130,41 +130,19 @@ static const struct emac_reg_write cdr_setting[] = { 
{END_MARKER,				END_MARKER},

};



static const struct emac_reg_write tx_rx_setting[][TX_RX_MAX_REG_CNT] = {

	/* EMAC_PHY_MAP_DEFAULT */

	{

		{EMAC_QSERDES_TX_BIST_MODE_LANENO,

			QSERDES_TX_BIST_MODE_LANENO},

		{EMAC_QSERDES_TX_TX_DRV_LVL,		TX_DRV_LVL_MUX |

			(QSERDES_TX_DRV_LVL_DEF << TX_DRV_LVL_SHFT)},

		{EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN,	EMP_EN_MUX | EMP_EN},

		{EMAC_QSERDES_TX_TX_EMP_POST1_LVL,	TX_EMP_POST1_LVL_MUX |

			(QSERDES_TX_EMP_POST1_LVL_DEF << TX_EMP_POST1_LVL_SHFT)

			},

		{EMAC_QSERDES_RX_RX_EQ_GAIN12,

			(QSERDES_RX_EQ_GAIN2_DEF << RX_EQ_GAIN2_SHFT) |

			(QSERDES_RX_EQ_GAIN1_DEF << RX_EQ_GAIN1_SHFT)},

		{EMAC_QSERDES_TX_LANE_MODE,

			QSERDES_TX_LANE_MODE_DEF},

		{END_MARKER,				END_MARKER}

	},

	/* EMAC_PHY_MAP_MDM9607 */

	{

		{EMAC_QSERDES_TX_BIST_MODE_LANENO,

			QSERDES_TX_BIST_MODE_LANENO},

static const struct emac_reg_write tx_rx_setting[] = {

{EMAC_QSERDES_TX_BIST_MODE_LANENO,	QSERDES_TX_BIST_MODE_LANENO},

{EMAC_QSERDES_TX_TX_DRV_LVL,		TX_DRV_LVL_MUX |

			(QSERDES_TX_DRV_LVL_MDM << TX_DRV_LVL_SHFT)},

			(QSERDES_TX_DRV_LVL << TX_DRV_LVL_SHFT)},

{EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN,	EMP_EN_MUX | EMP_EN},

{EMAC_QSERDES_TX_TX_EMP_POST1_LVL,	TX_EMP_POST1_LVL_MUX |

			(QSERDES_TX_EMP_POST1_LVL_MDM << TX_EMP_POST1_LVL_SHFT)

			},

			(QSERDES_TX_EMP_POST1_LVL << TX_EMP_POST1_LVL_SHFT)},

{EMAC_QSERDES_RX_RX_EQ_GAIN12,

			(QSERDES_RX_EQ_GAIN2_MDM << RX_EQ_GAIN2_SHFT) |

			(QSERDES_RX_EQ_GAIN1_MDM << RX_EQ_GAIN1_SHFT)},

			(QSERDES_RX_EQ_GAIN2 << RX_EQ_GAIN2_SHFT) |

			(QSERDES_RX_EQ_GAIN1 << RX_EQ_GAIN1_SHFT)},

{EMAC_QSERDES_TX_LANE_MODE,

			QSERDES_TX_LANE_MODE_MDM},

			QSERDES_TX_LANE_MODE},

{END_MARKER,				END_MARKER}

	}

};



static int emac_sgmii_v1_init(struct emac_adapter *adpt)
@@ -191,9 +169,7 @@ static int emac_sgmii_v1_init(struct emac_adapter *adpt) 
		sgmii->base,

		(const struct emac_reg_write *)&pll_setting[phy->board_id]);

	emac_reg_write_all(sgmii->base, cdr_setting);

	emac_reg_write_all(

		sgmii->base,

		(const struct emac_reg_write *)&tx_rx_setting[phy->board_id]);

	emac_reg_write_all(sgmii->base, tx_rx_setting);



	/* Ensure SerDes engine configuration is written to hw before powering

	 * it up