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Commit 962f480e authored by Chris Dearman's avatar Chris Dearman Committed by Ralf Baechle
Browse files

[MIPS] All MIPS32 processors support64-bit physical addresses.



Still, only the 4K may actually implement it.

Signed-off-by: default avatarChris Dearman <chris@mips.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 0bfa130e
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+1 −1
Original line number Original line Diff line number Diff line
@@ -142,7 +142,7 @@ void *kmap_coherent(struct page *page, unsigned long addr)
#endif
#endif
	vaddr = __fix_to_virt(FIX_CMAP_END - idx);
	vaddr = __fix_to_virt(FIX_CMAP_END - idx);
	pte = mk_pte(page, PAGE_KERNEL);
	pte = mk_pte(page, PAGE_KERNEL);
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
	entrylo = pte.pte_high;
	entrylo = pte.pte_high;
#else
#else
	entrylo = pte_val(pte) >> 6;
	entrylo = pte_val(pte) >> 6;
+1 −1
Original line number Original line Diff line number Diff line
@@ -299,7 +299,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
	idx = read_c0_index();
	idx = read_c0_index();
	ptep = pte_offset_map(pmdp, address);
	ptep = pte_offset_map(pmdp, address);


#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
	write_c0_entrylo0(ptep->pte_high);
	write_c0_entrylo0(ptep->pte_high);
	ptep++;
	ptep++;
	write_c0_entrylo1(ptep->pte_high);
	write_c0_entrylo1(ptep->pte_high);
+2 −2
Original line number Original line Diff line number Diff line
@@ -107,7 +107,7 @@ static inline void pmd_clear(pmd_t *pmdp)
	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
}
}


#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
#define pte_page(x)		pfn_to_page(pte_pfn(x))
#define pte_page(x)		pfn_to_page(pte_pfn(x))
#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))
#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))
static inline pte_t
static inline pte_t
@@ -130,7 +130,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
#define pte_pfn(x)		((unsigned long)((x).pte >> PAGE_SHIFT))
#define pte_pfn(x)		((unsigned long)((x).pte >> PAGE_SHIFT))
#define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
#endif
#endif
#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */


#define __pgd_offset(address)	pgd_index(address)
#define __pgd_offset(address)	pgd_index(address)
#define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
#define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+3 −3
Original line number Original line Diff line number Diff line
@@ -32,7 +32,7 @@
 * unpredictable things.  The code (when it is written) to deal with
 * unpredictable things.  The code (when it is written) to deal with
 * this problem will be in the update_mmu_cache() code for the r4k.
 * this problem will be in the update_mmu_cache() code for the r4k.
 */
 */
#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)


#define _PAGE_PRESENT               (1<<6)  /* implemented in software */
#define _PAGE_PRESENT               (1<<6)  /* implemented in software */
#define _PAGE_READ                  (1<<7)  /* implemented in software */
#define _PAGE_READ                  (1<<7)  /* implemented in software */
@@ -122,7 +122,7 @@


#endif
#endif
#endif
#endif
#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */


#define __READABLE	(_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
#define __READABLE	(_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
#define __WRITEABLE	(_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
#define __WRITEABLE	(_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -139,7 +139,7 @@
#define PAGE_CACHABLE_DEFAULT	_CACHE_CACHABLE_COW
#define PAGE_CACHABLE_DEFAULT	_CACHE_CACHABLE_COW
#endif
#endif


#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
#define CONF_CM_DEFAULT		(PAGE_CACHABLE_DEFAULT >> 3)
#define CONF_CM_DEFAULT		(PAGE_CACHABLE_DEFAULT >> 3)
#else
#else
#define CONF_CM_DEFAULT		(PAGE_CACHABLE_DEFAULT >> 9)
#define CONF_CM_DEFAULT		(PAGE_CACHABLE_DEFAULT >> 9)
+3 −3
Original line number Original line Diff line number Diff line
@@ -79,7 +79,7 @@ extern void paging_init(void);
#define pmd_page(pmd)		(pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
#define pmd_page(pmd)		(pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
#define pmd_page_vaddr(pmd)	pmd_val(pmd)
#define pmd_page_vaddr(pmd)	pmd_val(pmd)


#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)


#define pte_none(pte)		(!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
#define pte_none(pte)		(!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
#define pte_present(pte)	((pte).pte_low & _PAGE_PRESENT)
#define pte_present(pte)	((pte).pte_low & _PAGE_PRESENT)
@@ -182,7 +182,7 @@ extern pgd_t swapper_pg_dir[];
 * The following only work if pte_present() is true.
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 * Undefined behaviour if not..
 */
 */
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
static inline int pte_write(pte_t pte)	{ return pte.pte_low & _PAGE_WRITE; }
static inline int pte_write(pte_t pte)	{ return pte.pte_low & _PAGE_WRITE; }
static inline int pte_dirty(pte_t pte)	{ return pte.pte_low & _PAGE_MODIFIED; }
static inline int pte_dirty(pte_t pte)	{ return pte.pte_low & _PAGE_MODIFIED; }
static inline int pte_young(pte_t pte)	{ return pte.pte_low & _PAGE_ACCESSED; }
static inline int pte_young(pte_t pte)	{ return pte.pte_low & _PAGE_ACCESSED; }
@@ -309,7 +309,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
 */
 */
#define mk_pte(page, pgprot)	pfn_pte(page_to_pfn(page), (pgprot))
#define mk_pte(page, pgprot)	pfn_pte(page_to_pfn(page), (pgprot))


#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
{
	pte.pte_low  &= _PAGE_CHG_MASK;
	pte.pte_low  &= _PAGE_CHG_MASK;