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Commit 961fb597 authored by Jerome Glisse's avatar Jerome Glisse Committed by Dave Airlie
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drm/radeon/kms: r600/r700 command stream checker 



This patch add cs checker to r600/r700 hw. Command stream checking
will rewrite some of the cs value in order to restrict GPU access
to BO size. This doesn't break old userspace but just enforce safe
value. It should break any things that was using the r600/r700 cs
ioctl to do forbidden things (malicious software), though we are
not aware of such things.

Here is the list of thing we check :
- enforcing resource size
- enforcing color buffer slice tile max, will restrict cb access
- enforcing db buffer slice tile max, will restrict db access

We don't check for shader bigger than the BO in which they are
supposed to be, such use would lead to GPU lockup and is harmless
from security POV, as far as we can tell (note that even checking
for this wouldn't prevent someone to write bogus shader that lead
to lockup).

This patch has received as much testing as humanly possible with
old userspace to check that it didn't break such configuration.
However not all the applications out there were tested, thus it
might broke some odd, rare applications.

[airlied: fix rules for cs checker for parallel builds]

Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 4c36b678

drivers/gpu/drm/radeon/Makefile

+5 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ $(obj)/r420_reg_safe.h: $(src)/reg_srcs/r420 $(obj)/mkregtable 
$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable

	$(call if_changed,mkregtable)



$(obj)/r600_reg_safe.h: $(src)/reg_srcs/r600 $(obj)/mkregtable

	$(call if_changed,mkregtable)



$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h



$(obj)/r200.o: $(obj)/r200_reg_safe.h
@@ -42,6 +45,8 @@ $(obj)/r420.o: $(obj)/r420_reg_safe.h 


$(obj)/rs600.o: $(obj)/rs600_reg_safe.h



$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h



radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \

	radeon_irq.o r300_cmdbuf.o r600_cp.o

# add KMS driver

drivers/gpu/drm/radeon/r600.c

+6 −0
Original line number Diff line number Diff line
@@ -1077,21 +1077,27 @@ void r600_gpu_init(struct radeon_device *rdev) 
	switch (rdev->config.r600.max_tile_pipes) {

	case 1:

		tiling_config |= PIPE_TILING(0);

		rdev->config.r600.tiling_npipes = 1;

		break;

	case 2:

		tiling_config |= PIPE_TILING(1);

		rdev->config.r600.tiling_npipes = 2;

		break;

	case 4:

		tiling_config |= PIPE_TILING(2);

		rdev->config.r600.tiling_npipes = 4;

		break;

	case 8:

		tiling_config |= PIPE_TILING(3);

		rdev->config.r600.tiling_npipes = 8;

		break;

	default:

		break;

	}

	rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);

	tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);

	tiling_config |= GROUP_SIZE(0);

	rdev->config.r600.tiling_group_size = 256;

	tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;

	if (tmp > 3) {

		tiling_config |= ROW_TILING(3);

drivers/gpu/drm/radeon/r600_cp.c

+31 −0
Original line number Diff line number Diff line
@@ -873,6 +873,17 @@ static void r600_gfx_init(struct drm_device *dev, 
	RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);

	RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));

	RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));

	if (gb_tiling_config & 0xc0) {

		dev_priv->r600_group_size = 512;

	} else {

		dev_priv->r600_group_size = 256;

	}

	dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);

	if (gb_tiling_config & 0x30) {

		dev_priv->r600_nbanks = 8;

	} else {

		dev_priv->r600_nbanks = 4;

	}



	RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);

	RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
@@ -1444,6 +1455,17 @@ static void r700_gfx_init(struct drm_device *dev, 
	RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);

	RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));

	RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));

	if (gb_tiling_config & 0xc0) {

		dev_priv->r600_group_size = 512;

	} else {

		dev_priv->r600_group_size = 256;

	}

	dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);

	if (gb_tiling_config & 0x30) {

		dev_priv->r600_nbanks = 8;

	} else {

		dev_priv->r600_nbanks = 4;

	}



	RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);

	RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
@@ -2526,3 +2548,12 @@ out: 
	mutex_unlock(&dev_priv->cs_mutex);

	return r;

}



void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size)

{

	struct drm_radeon_private *dev_priv = dev->dev_private;



	*npipes = dev_priv->r600_npipes;

	*nbanks = dev_priv->r600_nbanks;

	*group_size = dev_priv->r600_group_size;

}

drivers/gpu/drm/radeon/r600_cs.c

+698 −128

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drivers/gpu/drm/radeon/r600d.h

+466 −1

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