Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9613c02b authored by Archit Taneja's avatar Archit Taneja Committed by Tomi Valkeinen
Browse files

OMAP4: DSS2: Register configuration changes for DSI 



The following changes have changed from OMAP3 to OMAP4 DSI:
-The register field DSI_PLL_FREQSEL in DSI_PLL_CONFIGURATION2 has been removed.
-DCS_CMD_ENABLE and DCS_CMD_CODE bits have been moved from DSI_CTRL to
DSI_VC_CTRLi, hence the control of the bits is available per VC.
-DSI LDO powergood notification doesn't work on OMAP4. This is mentioned in
OMAP4 errata revision 1.8(Errata 1.76).
-OCP_WIDTH register field is included in DSI_VC_CTRL.
-The SCP clock is also required to access DSI PLL registers

Introduce dss features for these changes so that DSI runs on both OMAP3 and
OMAP4.

Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 2783fa84

drivers/video/omap2/dss/dsi.c

+39 −21
Original line number Diff line number Diff line
@@ -1275,7 +1275,7 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) 
{

	int r = 0;

	u32 l;

	int f;

	int f = 0;

	u8 regn_start, regn_end, regm_start, regm_end;

	u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
@@ -1349,18 +1349,18 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) 
	dsi_write_reg(DSI_PLL_CONFIGURATION1, l);



	BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max);

	if (cinfo->fint < 1000000)

		f = 0x3;

	else if (cinfo->fint < 1250000)

		f = 0x4;

	else if (cinfo->fint < 1500000)

		f = 0x5;

	else if (cinfo->fint < 1750000)

		f = 0x6;

	else

		f = 0x7;



	if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {

		f = cinfo->fint < 1000000 ? 0x3 :

			cinfo->fint < 1250000 ? 0x4 :

			cinfo->fint < 1500000 ? 0x5 :

			cinfo->fint < 1750000 ? 0x6 :

			0x7;

	}



	l = dsi_read_reg(DSI_PLL_CONFIGURATION2);



	if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))

		l = FLD_MOD(l, f, 4, 1);	/* DSI_PLL_FREQSEL */

	l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,

			11, 11);		/* DSI_PLL_CLKSEL */
@@ -1877,9 +1877,6 @@ static int dsi_complexio_init(struct omap_dss_device *dssdev) 


	DSSDBG("dsi_complexio_init\n");



	/* CIO_CLK_ICG, enable L3 clk to CIO */

	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);



	/* A dummy read using the SCP interface to any DSIPHY register is

	 * required after DSIPHY reset to complete the reset of the DSI complex

	 * I/O. */
@@ -1904,11 +1901,13 @@ static int dsi_complexio_init(struct omap_dss_device *dssdev) 
		goto err;

	}



	if (dss_has_feature(FEAT_DSI_LDO_STATUS)) {

		if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {

			DSSERR("ComplexIO LDO power down.\n");

			r = -ENODEV;

			goto err;

		}

	}



	dsi_complexio_timings();
@@ -2074,6 +2073,8 @@ static void dsi_vc_initial_config(int channel) 
	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */

	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */

	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */

	if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))

		r = FLD_MOD(r, 3, 11, 10);	/* OCP_WIDTH = 32 bit */



	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */

	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
@@ -2098,6 +2099,10 @@ static int dsi_vc_config_l4(int channel) 


	REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */



	/* DCS_CMD_ENABLE */

	if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))

		REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 30, 30);



	dsi_vc_enable(channel, 1);



	dsi.vc[channel].mode = DSI_VC_MODE_L4;
@@ -2122,6 +2127,10 @@ static int dsi_vc_config_vp(int channel) 


	REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */



	/* DCS_CMD_ENABLE */

	if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))

		REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 30, 30);



	dsi_vc_enable(channel, 1);



	dsi.vc[channel].mode = DSI_VC_MODE_VP;
@@ -2777,8 +2786,11 @@ static int dsi_proto_config(struct omap_dss_device *dssdev) 
	r = FLD_MOD(r, 2, 13, 12);	/* LINE_BUFFER, 2 lines */

	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */

	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */

	if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {

		r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */

	r = FLD_MOD(r, 0, 25, 25);	/* DCS_CMD_CODE, 1=start, 0=continue */

		/* DCS_CMD_CODE, 1=start, 0=continue */

		r = FLD_MOD(r, 0, 25, 25);

	}



	dsi_write_reg(DSI_CTRL, r);
@@ -3375,6 +3387,10 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev) 
{

	int r;



	/* The SCPClk is required for both PLL and CIO registers on OMAP4 */

	/* CIO_CLK_ICG, enable L3 clk to CIO */

	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);



	_dsi_print_reset_status();



	r = dsi_pll_init(dssdev, true, true);
@@ -3387,6 +3403,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev) 


	dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);

	dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);

	dss_select_lcd_clk_source(dssdev->manager->id,

		DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);



	DSSDBG("PLL OK\n");

drivers/video/omap2/dss/dss_features.c

+6 −3
Original line number Diff line number Diff line
@@ -252,7 +252,8 @@ static struct omap_dss_features omap3430_dss_features = { 
		FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |

		FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |

		FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |

		FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF,

		FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |

		FEAT_DSI_PLL_FREQSEL | FEAT_DSI_LDO_STATUS,



	.num_mgrs = 2,

	.num_ovls = 3,
@@ -271,7 +272,8 @@ static struct omap_dss_features omap3630_dss_features = { 
		FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |

		FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |

		FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |

		FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG,

		FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |

		FEAT_DSI_PLL_FREQSEL |FEAT_DSI_LDO_STATUS,



	.num_mgrs = 2,

	.num_ovls = 3,
@@ -289,7 +291,8 @@ static struct omap_dss_features omap4_dss_features = { 
	.has_feature	=

		FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |

		FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |

		FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC,

		FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |

		FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH,



	.num_mgrs = 3,

	.num_ovls = 3,

drivers/video/omap2/dss/dss_features.h

+18 −14
Original line number Diff line number Diff line
@@ -42,6 +42,10 @@ enum dss_feat_id { 
	FEAT_LCD_CLK_SRC		= 1 << 12,

	/* DSI-PLL power command 0x3 is not working */

	FEAT_DSI_PLL_PWR_BUG		= 1 << 13,

	FEAT_DSI_PLL_FREQSEL		= 1 << 14,

	FEAT_DSI_LDO_STATUS		= 1 << 15,

	FEAT_DSI_DCS_CMD_CONFIG_VC	= 1 << 16,

	FEAT_DSI_VC_OCP_WIDTH		= 1 << 17,

};



/* DSS register field id */