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Commit 94f743e4 authored by Paul Mackerras's avatar Paul Mackerras Committed by Greg Kroah-Hartman
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KVM: PPC: Book3S HV: Save/restore host values of debug registers 



commit 7ceaa6dcd8c6f59588428cec37f3c8093dd1011f upstream.

At present, HV KVM on POWER8 and POWER9 machines loses any instruction
or data breakpoint set in the host whenever a guest is run.
Instruction breakpoints are currently only used by xmon, but ptrace
and the perf_event subsystem can set data breakpoints as well as xmon.

To fix this, we save the host values of the debug registers (CIABR,
DAWR and DAWRX) before entering the guest and restore them on exit.
To provide space to save them in the stack frame, we expand the stack
frame allocated by kvmppc_hv_entry() from 112 to 144 bytes.

[paulus@ozlabs.org - Adjusted stack offsets since we aren't saving
 POWER9-specific registers.]

Fixes: b005255e ("KVM: PPC: Book3S HV: Context-switch new POWER8 SPRs", 2014-01-08)
Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 1c3ab876

arch/powerpc/kvm/book3s_hv_rmhandlers.S

+30 −5
Original line number Diff line number Diff line
@@ -36,6 +36,12 @@ 
#define NAPPING_CEDE	1

#define NAPPING_NOVCPU	2



/* Stack frame offsets for kvmppc_hv_entry */

#define SFS			112

#define STACK_SLOT_CIABR	(SFS-16)

#define STACK_SLOT_DAWR		(SFS-24)

#define STACK_SLOT_DAWRX	(SFS-32)



/*

 * Call kvmppc_hv_entry in real mode.

 * Must be called with interrupts hard-disabled.
@@ -360,7 +366,7 @@ kvmppc_hv_entry: 
	 */

	mflr	r0

	std	r0, PPC_LR_STKOFF(r1)

	stdu	r1, -112(r1)

	stdu	r1, -SFS(r1)



	/* Save R1 in the PACA */

	std	r1, HSTATE_HOST_R1(r13)
@@ -618,6 +624,16 @@ BEGIN_FTR_SECTION 
	mtspr	SPRN_SPURR,r8

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)



	/* Save host values of some registers */

BEGIN_FTR_SECTION

	mfspr	r5, SPRN_CIABR

	mfspr	r6, SPRN_DAWR

	mfspr	r7, SPRN_DAWRX

	std	r5, STACK_SLOT_CIABR(r1)

	std	r6, STACK_SLOT_DAWR(r1)

	std	r7, STACK_SLOT_DAWRX(r1)

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)



BEGIN_FTR_SECTION

	/* Set partition DABR */

	/* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
@@ -1180,8 +1196,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 
	 */

	li	r0, 0

	mtspr	SPRN_IAMR, r0

	mtspr	SPRN_CIABR, r0

	mtspr	SPRN_DAWRX, r0

	mtspr	SPRN_PSPB, r0

	mtspr	SPRN_TCSCR, r0

	mtspr	SPRN_WORT, r0
@@ -1358,6 +1372,17 @@ hdec_soon: /* r12 = trap, r13 = paca */ 
BEGIN_FTR_SECTION

	b	32f

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)



	/* Restore host values of some registers */

BEGIN_FTR_SECTION

	ld	r5, STACK_SLOT_CIABR(r1)

	ld	r6, STACK_SLOT_DAWR(r1)

	ld	r7, STACK_SLOT_DAWRX(r1)

	mtspr	SPRN_CIABR, r5

	mtspr	SPRN_DAWR, r6

	mtspr	SPRN_DAWRX, r7

END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)



	/*

	 * POWER7 guest -> host partition switch code.

	 * We don't have to lock against tlbies but we do
@@ -1584,8 +1609,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 
	li	r0, KVM_GUEST_MODE_NONE

	stb	r0, HSTATE_IN_GUEST(r13)



	ld	r0, 112+PPC_LR_STKOFF(r1)

	addi	r1, r1, 112

	ld	r0, SFS+PPC_LR_STKOFF(r1)

	addi	r1, r1, SFS

	mtlr	r0

	blr