Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394-2.6

M:	viro@zeniv.linux.org.uk

S:	Maintained

FIREWIRE SUBSYSTEM

FIREWIRE SUBSYSTEM (drivers/firewire, <linux/firewire*.h>)

P:	Kristian Hoegsberg, Stefan Richter

M:	krh@redhat.com, stefanr@s5r6.in-berlin.de

L:	linux1394-devel@lists.sourceforge.net

L:	linux-scsi@vger.kernel.org

S:	Orphan

IEEE 1394 SUBSYSTEM

IEEE 1394 SUBSYSTEM (drivers/ieee1394)

P:	Ben Collins

M:	ben.collins@ubuntu.com

P:	Stefan Richter

	event->closure	     = client->bus_reset_closure;

	event->type          = FW_CDEV_EVENT_BUS_RESET;

	event->generation    = client->device->generation;

	smp_rmb();           /* node_id must not be older than generation */

	event->node_id       = client->device->node_id;

	event->local_node_id = card->local_node->node_id;

	event->bm_node_id    = 0; /* FIXME: We don't track the BM. */

	event->irm_node_id   = card->irm_node->node_id;

	event->root_node_id  = card->root_node->node_id;

	event->generation    = card->generation;

}

static void

#include <linux/idr.h>

#include <linux/rwsem.h>

#include <asm/semaphore.h>

#include <asm/system.h>

#include <linux/ctype.h>

#include "fw-transaction.h"

#include "fw-topology.h"

int fw_device_enable_phys_dma(struct fw_device *device)

{

	int generation = device->generation;

	/* device->node_id, accessed below, must not be older than generation */

	smp_rmb();

	return device->card->driver->enable_phys_dma(device->card,

						     device->node_id,

						     device->generation);

						     generation);

}

EXPORT_SYMBOL(fw_device_enable_phys_dma);

	complete(&callback_data->done);

}

static int read_rom(struct fw_device *device, int index, u32 * data)

static int

read_rom(struct fw_device *device, int generation, int index, u32 *data)

{

	struct read_quadlet_callback_data callback_data;

	struct fw_transaction t;

	u64 offset;

	/* device->node_id, accessed below, must not be older than generation */

	smp_rmb();

	init_completion(&callback_data.done);

	offset = 0xfffff0000400ULL + index * 4;

	fw_send_request(device->card, &t, TCODE_READ_QUADLET_REQUEST,

			device->node_id, device->generation, device->max_speed,

			device->node_id, generation, device->max_speed,

			offset, NULL, 4, complete_transaction, &callback_data);

	wait_for_completion(&callback_data.done);

	return callback_data.rcode;

}

static int read_bus_info_block(struct fw_device *device)

/*

 * Read the bus info block, perform a speed probe, and read all of the rest of

 * the config ROM.  We do all this with a cached bus generation.  If the bus

 * generation changes under us, read_bus_info_block will fail and get retried.

 * It's better to start all over in this case because the node from which we

 * are reading the ROM may have changed the ROM during the reset.

 */

static int read_bus_info_block(struct fw_device *device, int generation)

{

	static u32 rom[256];

	u32 stack[16], sp, key;

	/* First read the bus info block. */

	for (i = 0; i < 5; i++) {

		if (read_rom(device, i, &rom[i]) != RCODE_COMPLETE)

		if (read_rom(device, generation, i, &rom[i]) != RCODE_COMPLETE)

			return -1;

		/*

		 * As per IEEE1212 7.2, during power-up, devices can

			device->max_speed = device->card->link_speed;

		while (device->max_speed > SCODE_100) {

			if (read_rom(device, 0, &dummy) == RCODE_COMPLETE)

			if (read_rom(device, generation, 0, &dummy) ==

			    RCODE_COMPLETE)

				break;

			device->max_speed--;

		}

			return -1;

		/* Read header quadlet for the block to get the length. */

		if (read_rom(device, i, &rom[i]) != RCODE_COMPLETE)

		if (read_rom(device, generation, i, &rom[i]) != RCODE_COMPLETE)

			return -1;

		end = i + (rom[i] >> 16) + 1;

		i++;

		 * it references another block, and push it in that case.

		 */

		while (i < end) {

			if (read_rom(device, i, &rom[i]) != RCODE_COMPLETE)

			if (read_rom(device, generation, i, &rom[i]) !=

			    RCODE_COMPLETE)

				return -1;

			if ((key >> 30) == 3 && (rom[i] >> 30) > 1 &&

			    sp < ARRAY_SIZE(stack))

	 * device.

	 */

	if (read_bus_info_block(device) < 0) {

	if (read_bus_info_block(device, device->generation) < 0) {

		if (device->config_rom_retries < MAX_RETRIES) {

			device->config_rom_retries++;

			schedule_delayed_work(&device->work, RETRY_DELAY);

		device = node->data;

		device->node_id = node->node_id;

		smp_wmb();  /* update node_id before generation */

		device->generation = card->generation;

		if (atomic_read(&device->state) == FW_DEVICE_RUNNING) {

			PREPARE_DELAYED_WORK(&device->work, fw_device_update);

	struct attribute *attrs[11];

};

/*

 * Note, fw_device.generation always has to be read before fw_device.node_id.

 * Use SMP memory barriers to ensure this.  Otherwise requests will be sent

 * to an outdated node_id if the generation was updated in the meantime due

 * to a bus reset.

 *

 * Likewise, fw-core will take care to update .node_id before .generation so

 * that whenever fw_device.generation is current WRT the actual bus generation,

 * fw_device.node_id is guaranteed to be current too.

 *

 * The same applies to fw_device.card->node_id vs. fw_device.generation.

 */

struct fw_device {

	atomic_t state;

	struct fw_node *node;

typedef int (*descriptor_callback_t)(struct context *ctx,

				     struct descriptor *d,

				     struct descriptor *last);

/*

 * A buffer that contains a block of DMA-able coherent memory used for

 * storing a portion of a DMA descriptor program.

 */

struct descriptor_buffer {

	struct list_head list;

	dma_addr_t buffer_bus;

	size_t buffer_size;

	size_t used;

	struct descriptor buffer[0];

};

struct context {

	struct fw_ohci *ohci;

	u32 regs;

	int total_allocation;

	struct descriptor *buffer;

	dma_addr_t buffer_bus;

	size_t buffer_size;

	struct descriptor *head_descriptor;

	struct descriptor *tail_descriptor;

	struct descriptor *tail_descriptor_last;

	struct descriptor *prev_descriptor;

	/*

	 * List of page-sized buffers for storing DMA descriptors.

	 * Head of list contains buffers in use and tail of list contains

	 * free buffers.

	 */

	struct list_head buffer_list;

	/*

	 * Pointer to a buffer inside buffer_list that contains the tail

	 * end of the current DMA program.

	 */

	struct descriptor_buffer *buffer_tail;

	/*

	 * The descriptor containing the branch address of the first

	 * descriptor that has not yet been filled by the device.

	 */

	struct descriptor *last;

	/*

	 * The last descriptor in the DMA program.  It contains the branch

	 * address that must be updated upon appending a new descriptor.

	 */

	struct descriptor *prev;

	descriptor_callback_t callback;

struct iso_context {

	struct fw_iso_context base;

	struct context context;

	int excess_bytes;

	void *header;

	size_t header_length;

};

#define SELF_ID_BUF_SIZE		0x800

#define OHCI_TCODE_PHY_PACKET		0x0e

#define OHCI_VERSION_1_1		0x010010

#define ISO_BUFFER_SIZE			(64 * 1024)

#define AT_BUFFER_SIZE			4096

static char ohci_driver_name[] = KBUILD_MODNAME;

static void context_tasklet(unsigned long data)

{

	struct context *ctx = (struct context *) data;

	struct fw_ohci *ohci = ctx->ohci;

	struct descriptor *d, *last;

	u32 address;

	int z;

	struct descriptor_buffer *desc;

	dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,

				ctx->buffer_size, DMA_TO_DEVICE);

	d    = ctx->tail_descriptor;

	last = ctx->tail_descriptor_last;

	desc = list_entry(ctx->buffer_list.next,

			struct descriptor_buffer, list);

	last = ctx->last;

	while (last->branch_address != 0) {

		struct descriptor_buffer *old_desc = desc;

		address = le32_to_cpu(last->branch_address);

		z = address & 0xf;

		d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);

		address &= ~0xf;

		/* If the branch address points to a buffer outside of the

		 * current buffer, advance to the next buffer. */

		if (address < desc->buffer_bus ||

				address >= desc->buffer_bus + desc->used)

			desc = list_entry(desc->list.next,

					struct descriptor_buffer, list);

		d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);

		last = find_branch_descriptor(d, z);

		if (!ctx->callback(ctx, d, last))

			break;

		ctx->tail_descriptor      = d;

		ctx->tail_descriptor_last = last;

		if (old_desc != desc) {

			/* If we've advanced to the next buffer, move the

			 * previous buffer to the free list. */

			unsigned long flags;

			old_desc->used = 0;

			spin_lock_irqsave(&ctx->ohci->lock, flags);

			list_move_tail(&old_desc->list, &ctx->buffer_list);

			spin_unlock_irqrestore(&ctx->ohci->lock, flags);

		}

		ctx->last = last;

	}

}

/*

 * Allocate a new buffer and add it to the list of free buffers for this

 * context.  Must be called with ohci->lock held.

 */

static int

context_add_buffer(struct context *ctx)

{

	struct descriptor_buffer *desc;

	dma_addr_t bus_addr;

	int offset;

	/*

	 * 16MB of descriptors should be far more than enough for any DMA

	 * program.  This will catch run-away userspace or DoS attacks.

	 */

	if (ctx->total_allocation >= 16*1024*1024)

		return -ENOMEM;

	desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,

			&bus_addr, GFP_ATOMIC);

	if (!desc)

		return -ENOMEM;

	offset = (void *)&desc->buffer - (void *)desc;

	desc->buffer_size = PAGE_SIZE - offset;

	desc->buffer_bus = bus_addr + offset;

	desc->used = 0;

	list_add_tail(&desc->list, &ctx->buffer_list);

	ctx->total_allocation += PAGE_SIZE;

	return 0;

}

static int

context_init(struct context *ctx, struct fw_ohci *ohci,

	     size_t buffer_size, u32 regs,

	     descriptor_callback_t callback)

	     u32 regs, descriptor_callback_t callback)

{

	ctx->ohci = ohci;

	ctx->regs = regs;

	ctx->buffer_size = buffer_size;

	ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);

	if (ctx->buffer == NULL)

	ctx->total_allocation = 0;

	INIT_LIST_HEAD(&ctx->buffer_list);

	if (context_add_buffer(ctx) < 0)

		return -ENOMEM;

	ctx->buffer_tail = list_entry(ctx->buffer_list.next,

			struct descriptor_buffer, list);

	tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);

	ctx->callback = callback;

	ctx->buffer_bus =

		dma_map_single(ohci->card.device, ctx->buffer,

			       buffer_size, DMA_TO_DEVICE);

	if (dma_mapping_error(ctx->buffer_bus)) {

		kfree(ctx->buffer);

		return -ENOMEM;

	}

	ctx->head_descriptor      = ctx->buffer;

	ctx->prev_descriptor      = ctx->buffer;

	ctx->tail_descriptor      = ctx->buffer;

	ctx->tail_descriptor_last = ctx->buffer;

	/*

	 * We put a dummy descriptor in the buffer that has a NULL

	 * branch address and looks like it's been sent.  That way we

	 * have a descriptor to append DMA programs to.  Also, the

	 * ring buffer invariant is that it always has at least one

	 * element so that head == tail means buffer full.

	 * have a descriptor to append DMA programs to.

	 */

	memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));

	ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);

	ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);

	ctx->head_descriptor++;

	memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));

	ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);

	ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);

	ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);

	ctx->last = ctx->buffer_tail->buffer;

	ctx->prev = ctx->buffer_tail->buffer;

	return 0;

}

context_release(struct context *ctx)

{

	struct fw_card *card = &ctx->ohci->card;

	struct descriptor_buffer *desc, *tmp;

	dma_unmap_single(card->device, ctx->buffer_bus,

			 ctx->buffer_size, DMA_TO_DEVICE);

	kfree(ctx->buffer);

	list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)

		dma_free_coherent(card->device, PAGE_SIZE, desc,

			desc->buffer_bus -

			((void *)&desc->buffer - (void *)desc));

}

/* Must be called with ohci->lock held */

static struct descriptor *

context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)

{

	struct descriptor *d, *tail, *end;

	struct descriptor *d = NULL;

	struct descriptor_buffer *desc = ctx->buffer_tail;

	d = ctx->head_descriptor;

	tail = ctx->tail_descriptor;

	end = ctx->buffer + ctx->buffer_size / sizeof(*d);

	if (z * sizeof(*d) > desc->buffer_size)

		return NULL;

	if (d + z <= tail) {

		goto has_space;

	} else if (d > tail && d + z <= end) {

		goto has_space;

	} else if (d > tail && ctx->buffer + z <= tail) {

		d = ctx->buffer;

		goto has_space;

	}

	if (z * sizeof(*d) > desc->buffer_size - desc->used) {

		/* No room for the descriptor in this buffer, so advance to the

		 * next one. */

		if (desc->list.next == &ctx->buffer_list) {

			/* If there is no free buffer next in the list,

			 * allocate one. */

			if (context_add_buffer(ctx) < 0)

				return NULL;

		}

		desc = list_entry(desc->list.next,

				struct descriptor_buffer, list);

		ctx->buffer_tail = desc;

	}

 has_space:

	d = desc->buffer + desc->used / sizeof(*d);

	memset(d, 0, z * sizeof(*d));

	*d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);

	*d_bus = desc->buffer_bus + desc->used;

	return d;

}

	struct fw_ohci *ohci = ctx->ohci;

	reg_write(ohci, COMMAND_PTR(ctx->regs),

		  le32_to_cpu(ctx->tail_descriptor_last->branch_address));

		  le32_to_cpu(ctx->last->branch_address));

	reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);

	reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);

	flush_writes(ohci);

			   struct descriptor *d, int z, int extra)

{

	dma_addr_t d_bus;

	struct descriptor_buffer *desc = ctx->buffer_tail;

	d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);

	d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);

	ctx->head_descriptor = d + z + extra;

	ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);

	ctx->prev_descriptor = find_branch_descriptor(d, z);

	dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,

				   ctx->buffer_size, DMA_TO_DEVICE);

	desc->used += (z + extra) * sizeof(*d);

	ctx->prev->branch_address = cpu_to_le32(d_bus | z);

	ctx->prev = find_branch_descriptor(d, z);

	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);

	flush_writes(ctx->ohci);

	if (unlikely(event & OHCI1394_postedWriteErr))

		fw_error("PCI posted write error\n");

	if (unlikely(event & OHCI1394_cycleTooLong)) {

		if (printk_ratelimit())

			fw_notify("isochronous cycle too long\n");

		reg_write(ohci, OHCI1394_LinkControlSet,

			  OHCI1394_LinkControl_cycleMaster);

	}

	if (event & OHCI1394_cycle64Seconds) {

		cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);

		if ((cycle_time & 0x80000000) == 0)

		  OHCI1394_RQPkt | OHCI1394_RSPkt |

		  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |

		  OHCI1394_isochRx | OHCI1394_isochTx |

		  OHCI1394_postedWriteErr | OHCI1394_cycle64Seconds |

		  OHCI1394_masterIntEnable);

		  OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |

		  OHCI1394_cycle64Seconds | OHCI1394_masterIntEnable);

	/* Activate link_on bit and contender bit in our self ID packets.*/

	if (ohci_update_phy_reg(card, 4, 0,

	void *p, *end;

	int i;

	if (db->first_res_count > 0 && db->second_res_count > 0)

	if (db->first_res_count > 0 && db->second_res_count > 0) {

		if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {

			/* This descriptor isn't done yet, stop iteration. */

			return 0;

		}

		ctx->excess_bytes -= le16_to_cpu(db->second_req_count);

	}

	header_length = le16_to_cpu(db->first_req_count) -

		le16_to_cpu(db->first_res_count);

		*(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));

		memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);

		i += ctx->base.header_size;

		ctx->excess_bytes +=

			(le32_to_cpu(*(u32 *)(p + 4)) >> 16) & 0xffff;

		p += ctx->base.header_size + 4;

	}

	ctx->header_length = i;

	ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -

		le16_to_cpu(db->second_res_count);

	if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {

		ir_header = (__le32 *) (db + 1);

		ctx->base.callback(&ctx->base,

{

	struct iso_context *ctx =

		container_of(context, struct iso_context, context);

	struct descriptor *pd = d + 1;

	struct descriptor *pd;

	__le32 *ir_header;

	size_t header_length;

	void *p, *end;

	int i, z;

	void *p;

	int i;

	if (pd->res_count == pd->req_count)

	for (pd = d; pd <= last; pd++) {

		if (pd->transfer_status)

			break;

	}

	if (pd > last)

		/* Descriptor(s) not done yet, stop iteration */

		return 0;

	header_length = le16_to_cpu(d->req_count);

	i   = ctx->header_length;

	z   = le32_to_cpu(pd->branch_address) & 0xf;

	p   = d + z;

	end = p + header_length;

	p   = last + 1;

	while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {

	if (ctx->base.header_size > 0 &&

			i + ctx->base.header_size <= PAGE_SIZE) {

		/*

		 * The iso header is byteswapped to little endian by

		 * the controller, but the remaining header quadlets

		 */

		*(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));

		memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);

		i += ctx->base.header_size;

		p += ctx->base.header_size + 4;

		ctx->header_length += ctx->base.header_size;

	}

	ctx->header_length = i;

	if (le16_to_cpu(pd->control) & DESCRIPTOR_IRQ_ALWAYS) {

		ir_header = (__le32 *) (d + z);

	if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {

		ir_header = (__le32 *) p;

		ctx->base.callback(&ctx->base,

				   le32_to_cpu(ir_header[0]) & 0xffff,

				   ctx->header_length, ctx->header,

		ctx->header_length = 0;

	}

	return 1;

}

	if (ctx->header == NULL)