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Commit 94475817 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Get rid of clk-map 



clk-map is another one of those historical oddities that we've had
forever. Luckily we have made the transition to clock-names for other
reasons so we already have all the information we need. Get rid of
clk-map and the associated infrastructure.

Change-Id: Ic0dedbad82c0a87ce98b37f9e66788fc16407ae6
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 11d1626c

Documentation/devicetree/bindings/gpu/adreno.txt

+0 −15
Original line number Diff line number Diff line
@@ -17,16 +17,6 @@ Required properties: 
- interrupt-names:	String property to describe the name of the interrupt.

- qcom,id:		An integer used as an identification number for the device.



- qcom,clk-map:		A bit map value for clocks controlled by kgsl.

				KGSL_CLK_SRC    0x00000001

				KGSL_CLK_CORE   0x00000002

				KGSL_CLK_IFACE  0x00000004

				KGSL_CLK_MEM    0x00000008

				KGSL_CLK_MEM_IFACE 0x00000010

				KGSL_CLK_AXI    0x00000020

				KGSL_CLK_RBBMTIMER 0x00000080

				KGSL_CLK_ALWAYSON 0x00000800



- clocks:		List of phandle and clock specifier pairs, one pair

			for each clock input to the device.

- clock-names:		List of clock input name strings sorted in the same
@@ -155,11 +145,6 @@ Example of A330 GPU in MSM8916: 
		qcom,idle-timeout = <8>;

		qcom,strtstp-sleepwake;



		/*

		 * Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM |

		 * KGSL_CLK_MEM_IFACE | KGSL_CLK_ALT_MEM_IFACE

		 */

		qcom,clk-map = <0x0000005E>;

		clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,

			<&clock_gcc clk_gcc_oxili_ahb_clk>,

			<&clock_gcc clk_gcc_oxili_gmem_clk>,

arch/arm/boot/dts/qcom/msm8952-gpu.dtsi

+0 −5
Original line number Diff line number Diff line
@@ -61,11 +61,6 @@ 
		qcom,idle-timeout = <8>; //<HZ/12>

		qcom,strtstp-sleepwake;



		/* Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM |

		KGSL_CLK_MEM_IFACE | KGSL_CLK_ALT_MEM_IFACE

		KGSL_CLK_RBBMTIMER */

		qcom,clk-map = <0x000001DE>;



		clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,

			<&clock_gcc clk_gcc_oxili_ahb_clk>,

			<&clock_gcc clk_gcc_oxili_gmem_clk>,

arch/arm/boot/dts/qcom/msm8996-gpu.dtsi

+0 −8
Original line number Diff line number Diff line
@@ -83,14 +83,6 @@ 
		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <4>;



		/*

		 * Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE

		 * KGSL_CLK_RBBMTIMER | KGSL_CLK_MEM_IFACE

		 * KGSL_CLK_ALT_MEM_IFACE | KGSL_CLK_MEM |

		 * KGSL_CLK_MX

		 */

		qcom,clk-map = <0x000004DE>;



		clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>,

			<&clock_gpu clk_gpu_ahb_clk>,

			<&clock_gpu clk_gpu_gx_rbbmtimer_clk>,

drivers/gpu/msm/adreno.c

+0 −4
Original line number Diff line number Diff line
@@ -998,10 +998,6 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, 
	device->pwrctrl.bus_control = of_property_read_bool(node,

		"qcom,bus-control");



	if (adreno_of_read_property(node, "qcom,clk-map",

		&device->pwrctrl.clk_map))

		return -EINVAL;



	return 0;

}

drivers/gpu/msm/kgsl_pwrctrl.c

+74 −106
Original line number Diff line number Diff line
@@ -54,65 +54,19 @@ 
#define DEFAULT_BUS_P 25

#define DEFAULT_BUS_DIV (100 / DEFAULT_BUS_P)



/* Clock map definitions */

#define KGSL_CLK_ALT_MEM_IFACE 0x00000040

#define KGSL_CLK_RBBMTIMER	0x00000080

#define KGSL_CLK_GFX_GTCU   0x00000100

#define KGSL_CLK_GFX_GTBU   0x00000200

#define KGSL_CLK_MX	0x00000400

#define KGSL_CLK_ALWAYSON   0x00000800



struct clk_pair {

	const char *name;

	uint map;

};



static struct clk_pair clks[KGSL_MAX_CLKS] = {

	{

		.name = "src_clk",

		.map = KGSL_CLK_SRC,

	},

	{

		.name = "core_clk",

		.map = KGSL_CLK_CORE,

	},

	{

		.name = "iface_clk",

		.map = KGSL_CLK_IFACE,

	},

	{

		.name = "mem_clk",

		.map = KGSL_CLK_MEM,

	},

	{

		.name = "mem_iface_clk",

		.map = KGSL_CLK_MEM_IFACE,

	},

	{

		.name = "alt_mem_iface_clk",

		.map = KGSL_CLK_ALT_MEM_IFACE,

	},

	{

		.name = "rbbmtimer_clk",

		.map = KGSL_CLK_RBBMTIMER,

	},

	{

		.name = "gtcu_clk",

		.map = KGSL_CLK_GFX_GTCU,

	},

	{

		.name = "gtbu_clk",

		.map = KGSL_CLK_GFX_GTBU,

	},

	{

		.name = "alwayson_clk",

		.map = KGSL_CLK_ALWAYSON,

	},

};



static struct clk_pair dummy_mx_clk = {

		.name = "mx_clk",

		.map = KGSL_CLK_MX,

/* Order deeply matters here because reasons. New entries go on the end */

static const char * const clocks[] = {

	"src_clk",

	"core_clk",

	"iface_clk",

	"mem_clk",

	"mem_iface_clk",

	"alt_mem_iface_clk",

	"rbbmtimer_clk",

	"gtcu_clk",

	"gtbu_clk",

	"gtcu_iface_clk",

	"alwayson_clk"

};



static unsigned int ib_votes[KGSL_MAX_BUSLEVELS];
@@ -1321,7 +1275,6 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state, 
			trace_kgsl_clk(device, state,

					kgsl_pwrctrl_active_freq(pwr));

			for (i = KGSL_MAX_CLKS - 1; i > 0; i--)

				if (pwr->grp_clks[i])

				clk_disable(pwr->grp_clks[i]);

			/* High latency clock maintenance. */

			if ((pwr->pwrlevels[0].gpu_freq > 0) &&
@@ -1329,7 +1282,6 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state, 
				(requested_state !=

						KGSL_STATE_DEEP_NAP)) {

				for (i = KGSL_MAX_CLKS - 1; i > 0; i--)

					if (pwr->grp_clks[i])

					clk_unprepare(pwr->grp_clks[i]);

				clk_set_rate(pwr->grp_clks[0],

					pwr->pwrlevels[pwr->num_pwrlevels - 1].
@@ -1338,7 +1290,6 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state, 
		} else if (requested_state == KGSL_STATE_SLEEP) {

			/* High latency clock maintenance. */

			for (i = KGSL_MAX_CLKS - 1; i > 0; i--)

				if (pwr->grp_clks[i])

				clk_unprepare(pwr->grp_clks[i]);

			if ((pwr->pwrlevels[0].gpu_freq > 0))

				clk_set_rate(pwr->grp_clks[0],
@@ -1359,13 +1310,11 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state, 
						[pwr->active_pwrlevel].

						gpu_freq);

				for (i = KGSL_MAX_CLKS - 1; i > 0; i--)

					if (pwr->grp_clks[i])

					clk_prepare(pwr->grp_clks[i]);

			}

			/* as last step, enable grp_clk

			   this is to let GPU interrupt to come */

			for (i = KGSL_MAX_CLKS - 1; i > 0; i--)

				if (pwr->grp_clks[i])

				clk_enable(pwr->grp_clks[i]);

		}

	}
@@ -1587,11 +1536,41 @@ static int get_regulators(struct kgsl_device *device) 
	return 0;

}



static int _get_clocks(struct kgsl_device *device)

{

	struct device *dev = &device->pdev->dev;

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;

	const char *name;

	struct property *prop;



	of_property_for_each_string(dev->of_node, "clock-names", prop, name) {

		int i;



		for (i = 0; i < KGSL_MAX_CLKS; i++) {

			if (pwr->grp_clks[i] || strcmp(clocks[i], name))

				continue;



			pwr->grp_clks[i] = devm_clk_get(dev, name);



			if (IS_ERR(pwr->grp_clks[i])) {

				int ret = PTR_ERR(pwr->grp_clks[i]);



				KGSL_CORE_ERR("Couldn't get clock: %s (%d)\n",

					name, ret);

				pwr->grp_clks[i] = NULL;

				return ret;

			}



			break;

		}

	}



	return 0;

}



int kgsl_pwrctrl_init(struct kgsl_device *device)

{

	int i, k, m, n = 0, result = 0;

	unsigned int rbbmtimer_freq;

	struct clk *clk;

	int i, k, m, n = 0, result;

	struct platform_device *pdev = device->pdev;

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;

	struct device_node *ocmem_bus_node;
@@ -1604,19 +1583,10 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 
	if (bus_scale_table == NULL)

		return -EINVAL;



	/*acquire clocks */

	for (i = 0; i < KGSL_MAX_CLKS; i++) {

		if (pwr->clk_map & clks[i].map) {

			clk = clk_get(&pdev->dev, clks[i].name);

			if (IS_ERR(clk)) {

				KGSL_PWR_ERR(device,

					"clk_get(%s) failed: %ld\n",

					clks[i].name, PTR_ERR(clk));

				return PTR_ERR(clk);

			}

			pwr->grp_clks[i] = clk;

		}

	}

	result = _get_clocks(device);

	if (result)

		return result;



	/* Make sure we have a source clk for freq setting */

	if (pwr->grp_clks[0] == NULL)

		pwr->grp_clks[0] = pwr->grp_clks[1];
@@ -1628,14 +1598,14 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 
	pwr->gx_retention = of_property_read_bool(pdev->dev.of_node,

						"qcom,gx-retention");

	if (pwr->gx_retention) {

		clk = clk_get(&pdev->dev, dummy_mx_clk.name);

		if (IS_ERR(clk)) {

		pwr->dummy_mx_clk = clk_get(&pdev->dev, "mx_clk");

		if (IS_ERR(pwr->dummy_mx_clk)) {

			pwr->gx_retention = 0;

			KGSL_PWR_ERR(device, "clk_get(%s) failed: %d\n",

				 dummy_mx_clk.name, (int)PTR_ERR(clk));

		} else

			pwr->dummy_mx_clk = clk;

			pwr->dummy_mx_clk = NULL;

			KGSL_CORE_ERR("Couldn't get clock: mx_clk\n");

		}

	}



	pwr->power_flags = BIT(KGSL_PWRFLAGS_RETENTION_ON);



	if (pwr->num_pwrlevels == 0) {
@@ -1652,17 +1622,19 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) 
	pwr->wakeup_maxpwrlevel = 0;



	for (i = 0; i < pwr->num_pwrlevels; i++) {

		if (pwr->pwrlevels[i].gpu_freq > 0)

			pwr->pwrlevels[i].gpu_freq =

				clk_round_rate(pwr->grp_clks[0],

					pwr->pwrlevels[i].gpu_freq);

		unsigned int freq = pwr->pwrlevels[i].gpu_freq;



		if (freq > 0)

			freq = clk_round_rate(pwr->grp_clks[0], freq);



		pwr->pwrlevels[i].gpu_freq = freq;

	}



	clk_set_rate(pwr->grp_clks[0], pwr->

			pwrlevels[pwr->num_pwrlevels - 1].gpu_freq);

	rbbmtimer_freq = clk_round_rate(pwr->grp_clks[6],

					KGSL_RBBMTIMER_CLK_FREQ);

	clk_set_rate(pwr->grp_clks[6], rbbmtimer_freq);

	clk_set_rate(pwr->grp_clks[0],

		pwr->pwrlevels[pwr->num_pwrlevels - 1].gpu_freq);



	clk_set_rate(pwr->grp_clks[6],

		clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ));



	result = get_regulators(device);

	if (result)
@@ -1813,13 +1785,9 @@ void kgsl_pwrctrl_close(struct kgsl_device *device) 
		}

	}



	for (i = 1; i < KGSL_MAX_CLKS; i++)

		if (pwr->grp_clks[i]) {

			clk_put(pwr->grp_clks[i]);

	for (i = 0; i < KGSL_MAX_REGULATORS; i++)

		pwr->grp_clks[i] = NULL;

		}



	pwr->grp_clks[0] = NULL;

	pwr->power_flags = 0;



	if (!IS_ERR_OR_NULL(pwr->sysfs_pwr_limit)) {