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Commit 93dfb40c authored by Chris Wilson's avatar Chris Wilson Committed by Keith Packard
Browse files

drm/i915: Rename agp_type to cache_level 



... to clarify just how we use it inside the driver and remove the
confusion of the poorly matching agp_type names. We still need to
translate through agp_type for interface into the fake AGP driver.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent e76d3630

drivers/gpu/drm/i915/i915_debugfs.c

+6 −5
Original line number Diff line number Diff line
@@ -106,11 +106,12 @@ static const char *get_tiling_flag(struct drm_i915_gem_object *obj) 
    }

}



static const char *agp_type_str(int type)

static const char *cache_level_str(int type)

{

	switch (type) {

	case 0: return " uncached";

	case 1: return " snooped";

	case I915_CACHE_NONE: return " uncached";

	case I915_CACHE_LLC: return " snooped (LLC)";

	case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";

	default: return "";

	}

}
@@ -127,7 +128,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 
		   obj->base.write_domain,

		   obj->last_rendering_seqno,

		   obj->last_fenced_seqno,

		   agp_type_str(obj->agp_type == AGP_USER_CACHED_MEMORY),

		   cache_level_str(obj->cache_level),

		   obj->dirty ? " dirty" : "",

		   obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");

	if (obj->base.name)
@@ -714,7 +715,7 @@ static void print_error_buffers(struct seq_file *m, 
			   dirty_flag(err->dirty),

			   purgeable_flag(err->purgeable),

			   ring_str(err->ring),

			   agp_type_str(err->agp_type));

			   cache_level_str(err->cache_level));



		if (err->name)

			seq_printf(m, " (name: %d)", err->name);

drivers/gpu/drm/i915/i915_drv.h

+9 −3
Original line number Diff line number Diff line
@@ -188,7 +188,7 @@ struct drm_i915_error_state { 
		u32 dirty:1;

		u32 purgeable:1;

		u32 ring:4;

		u32 agp_type:1;

		u32 cache_level:2;

	} *active_bo, *pinned_bo;

	u32 active_bo_count, pinned_bo_count;

	struct intel_overlay_error_state *overlay;
@@ -711,6 +711,12 @@ typedef struct drm_i915_private { 
	struct drm_property *broadcast_rgb_property;

} drm_i915_private_t;



enum i915_cache_level {

	I915_CACHE_NONE,

	I915_CACHE_LLC,

	I915_CACHE_LLC_MLC, /* gen6+ */

};



struct drm_i915_gem_object {

	struct drm_gem_object base;
@@ -797,6 +803,8 @@ struct drm_i915_gem_object { 
	unsigned int pending_fenced_gpu_access:1;

	unsigned int fenced_gpu_access:1;



	unsigned int cache_level:2;



	struct page **pages;



	/**
@@ -833,8 +841,6 @@ struct drm_i915_gem_object { 
	/** Record of address bit 17 of each page at last unbind. */

	unsigned long *bit_17;



	/** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */

	uint32_t agp_type;



	/**

	 * If present, while GEM_DOMAIN_CPU is in the read domain this array

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -3569,7 +3569,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;

	obj->base.read_domains = I915_GEM_DOMAIN_CPU;



	obj->agp_type = AGP_USER_MEMORY;

	obj->cache_level = I915_CACHE_NONE;

	obj->base.driver_private = NULL;

	obj->fence_reg = I915_FENCE_REG_NONE;

	INIT_LIST_HEAD(&obj->mm_list);

drivers/gpu/drm/i915/i915_gem_gtt.c

+29 −6
Original line number Diff line number Diff line
@@ -29,6 +29,26 @@ 
#include "i915_trace.h"

#include "intel_drv.h"



/* XXX kill agp_type! */

static unsigned int cache_level_to_agp_type(struct drm_device *dev,

					    enum i915_cache_level cache_level)

{

	switch (cache_level) {

	case I915_CACHE_LLC_MLC:

		if (INTEL_INFO(dev)->gen >= 6)

			return AGP_USER_CACHED_MEMORY_LLC_MLC;

		/* Older chipsets do not have this extra level of CPU

		 * cacheing, so fallthrough and request the PTE simply

		 * as cached.

		 */

	case I915_CACHE_LLC:

		return AGP_USER_CACHED_MEMORY;

	default:

	case I915_CACHE_NONE:

		return AGP_USER_MEMORY;

	}

}



void i915_gem_restore_gtt_mappings(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -39,6 +59,9 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) 
			      (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);



	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {

		unsigned int agp_type =

			cache_level_to_agp_type(dev, obj->cache_level);



		i915_gem_clflush_object(obj);



		if (dev_priv->mm.gtt->needs_dmar) {
@@ -46,15 +69,14 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) 


			intel_gtt_insert_sg_entries(obj->sg_list,

						    obj->num_sg,

						    obj->gtt_space->start

							>> PAGE_SHIFT,

						    obj->agp_type);

						    obj->gtt_space->start >> PAGE_SHIFT,

						    agp_type);

		} else

			intel_gtt_insert_pages(obj->gtt_space->start

						   >> PAGE_SHIFT,

					       obj->base.size >> PAGE_SHIFT,

					       obj->pages,

					       obj->agp_type);

					       agp_type);

	}



	intel_gtt_chipset_flush();
@@ -64,6 +86,7 @@ int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj) 
{

	struct drm_device *dev = obj->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);

	int ret;



	if (dev_priv->mm.gtt->needs_dmar) {
@@ -77,12 +100,12 @@ int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj) 
		intel_gtt_insert_sg_entries(obj->sg_list,

					    obj->num_sg,

					    obj->gtt_space->start >> PAGE_SHIFT,

					    obj->agp_type);

					    agp_type);

	} else

		intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,

				       obj->base.size >> PAGE_SHIFT,

				       obj->pages,

				       obj->agp_type);

				       agp_type);



	return 0;

}

drivers/gpu/drm/i915/i915_irq.c

+1 −1
Original line number Diff line number Diff line
@@ -676,7 +676,7 @@ static u32 capture_bo_list(struct drm_i915_error_buffer *err, 
		err->dirty = obj->dirty;

		err->purgeable = obj->madv != I915_MADV_WILLNEED;

		err->ring = obj->ring ? obj->ring->id : 0;

		err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY;

		err->cache_level = obj->cache_level;



		if (++i == count)

			break;