Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/tg3-2.6 (931b11be) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/net/tg3.c

+101 −85

Original line number	Diff line number	Diff line
		@@ -68,8 +68,8 @@

		#define DRV_MODULE_NAME "tg3"
		#define PFX DRV_MODULE_NAME ": "
		#define DRV_MODULE_VERSION "3.45"
		#define DRV_MODULE_RELDATE "Dec 13, 2005"
		#define DRV_MODULE_VERSION "3.46"
		#define DRV_MODULE_RELDATE "Dec 19, 2005"

		#define TG3_DEF_MAC_MODE 0
		#define TG3_DEF_RX_MODE 0
		@@ -341,6 +341,16 @@ static struct {
		{ "interrupt test (offline)" },
		};

		static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
		{
		writel(val, tp->regs + off);
		}

		static u32 tg3_read32(struct tg3 *tp, u32 off)
		{
		return (readl(tp->regs + off));
		}

		static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
		{
		unsigned long flags;
		@@ -411,13 +421,29 @@ static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
		return val;
		}

		static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
		/* usec_wait specifies the wait time in usec when writing to certain registers
		* where it is unsafe to read back the register without some delay.
		* GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
		* TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
		*/
		static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
		{
		if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) \|\|
		(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
		/* Non-posted methods */
		tp->write32(tp, off, val);
		if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) &&
		!(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) &&
		!(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
		tp->read32(tp, off); /* flush */
		else {
		/* Posted method */
		tg3_write32(tp, off, val);
		if (usec_wait)
		udelay(usec_wait);
		tp->read32(tp, off);
		}
		/* Wait again after the read for the posted method to guarantee that
		* the wait time is met.
		*/
		if (usec_wait)
		udelay(usec_wait);
		}

		static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
		@@ -438,16 +464,6 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
		readl(mbox);
		}

		static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
		{
		writel(val, tp->regs + off);
		}

		static u32 tg3_read32(struct tg3 *tp, u32 off)
		{
		return (readl(tp->regs + off));
		}

		#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
		#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
		#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
		@@ -455,7 +471,8 @@ static u32 tg3_read32(struct tg3 *tp, u32 off)
		#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)

		#define tw32(reg,val) tp->write32(tp, reg, val)
		#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
		#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
		#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
		#define tr32(reg) tp->read32(tp, reg)

		static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
		@@ -595,21 +612,19 @@ static void tg3_switch_clocks(struct tg3 *tp)

		if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
		if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
		tw32_f(TG3PCI_CLOCK_CTRL,
		clock_ctrl \| CLOCK_CTRL_625_CORE);
		udelay(40);
		tw32_wait_f(TG3PCI_CLOCK_CTRL,
		clock_ctrl \| CLOCK_CTRL_625_CORE, 40);
		}
		} else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
		tw32_f(TG3PCI_CLOCK_CTRL,
		tw32_wait_f(TG3PCI_CLOCK_CTRL,
		clock_ctrl \|
		(CLOCK_CTRL_44MHZ_CORE \| CLOCK_CTRL_ALTCLK));
		udelay(40);
		tw32_f(TG3PCI_CLOCK_CTRL,
		clock_ctrl \| (CLOCK_CTRL_ALTCLK));
		udelay(40);
		(CLOCK_CTRL_44MHZ_CORE \| CLOCK_CTRL_ALTCLK),
		40);
		tw32_wait_f(TG3PCI_CLOCK_CTRL,
		clock_ctrl \| (CLOCK_CTRL_ALTCLK),
		40);
		}
		tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
		udelay(40);
		tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
		}

		#define PHY_BUSY_LOOPS 5000
		@@ -1017,39 +1032,50 @@ static void tg3_frob_aux_power(struct tg3 *tp)
		if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
		return;

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
		tp_peer = pci_get_drvdata(tp->pdev_peer);
		if (!tp_peer)
		if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) \|\|
		(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
		struct net_device *dev_peer;

		dev_peer = pci_get_drvdata(tp->pdev_peer);
		if (!dev_peer)
		BUG();
		tp_peer = netdev_priv(dev_peer);
		}


		if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 \|\|
		(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 \|\|
		(tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 \|\|
		(tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 \|\|
		GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		(GRC_LCLCTRL_GPIO_OE0 \|
		GRC_LCLCTRL_GPIO_OE1 \|
		GRC_LCLCTRL_GPIO_OE2 \|
		GRC_LCLCTRL_GPIO_OUTPUT0 \|
		GRC_LCLCTRL_GPIO_OUTPUT1));
		udelay(100);
		GRC_LCLCTRL_GPIO_OUTPUT1),
		100);
		} else {
		u32 no_gpio2;
		u32 grc_local_ctrl;
		u32 grc_local_ctrl = 0;

		if (tp_peer != tp &&
		(tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
		return;

		/* Workaround to prevent overdrawing Amps. */
		if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
		ASIC_REV_5714) {
		grc_local_ctrl \|= GRC_LCLCTRL_GPIO_OE3;
		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		grc_local_ctrl, 100);
		}

		/* On 5753 and variants, GPIO2 cannot be used. */
		no_gpio2 = tp->nic_sram_data_cfg &
		NIC_SRAM_DATA_CFG_NO_GPIO2;

		grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 \|
		grc_local_ctrl \|= GRC_LCLCTRL_GPIO_OE0 \|
		GRC_LCLCTRL_GPIO_OE1 \|
		GRC_LCLCTRL_GPIO_OE2 \|
		GRC_LCLCTRL_GPIO_OUTPUT1 \|
		@@ -1058,21 +1084,18 @@ static void tg3_frob_aux_power(struct tg3 *tp)
		grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 \|
		GRC_LCLCTRL_GPIO_OUTPUT2);
		}
		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		grc_local_ctrl);
		udelay(100);
		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		grc_local_ctrl, 100);

		grc_local_ctrl \|= GRC_LCLCTRL_GPIO_OUTPUT0;

		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		grc_local_ctrl);
		udelay(100);
		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		grc_local_ctrl, 100);

		if (!no_gpio2) {
		grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		grc_local_ctrl);
		udelay(100);
		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		grc_local_ctrl, 100);
		}
		}
		} else {
		@@ -1082,19 +1105,16 @@ static void tg3_frob_aux_power(struct tg3 *tp)
		(tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
		return;

		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		(GRC_LCLCTRL_GPIO_OE1 \|
		GRC_LCLCTRL_GPIO_OUTPUT1));
		udelay(100);
		GRC_LCLCTRL_GPIO_OUTPUT1), 100);

		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		(GRC_LCLCTRL_GPIO_OE1));
		udelay(100);
		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		GRC_LCLCTRL_GPIO_OE1, 100);

		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl \|
		(GRC_LCLCTRL_GPIO_OE1 \|
		GRC_LCLCTRL_GPIO_OUTPUT1));
		udelay(100);
		GRC_LCLCTRL_GPIO_OUTPUT1), 100);
		}
		}
		}
		@@ -1137,10 +1157,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
		udelay(100); /* Delay after power state change */

		/* Switch out of Vaux if it is not a LOM */
		if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
		udelay(100);
		}
		if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);

		return 0;

		@@ -1239,10 +1257,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
		base_val \|= (CLOCK_CTRL_RXCLK_DISABLE \|
		CLOCK_CTRL_TXCLK_DISABLE);

		tw32_f(TG3PCI_CLOCK_CTRL, base_val \|
		CLOCK_CTRL_ALTCLK \|
		CLOCK_CTRL_PWRDOWN_PLL133);
		udelay(40);
		tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val \| CLOCK_CTRL_ALTCLK \|
		CLOCK_CTRL_PWRDOWN_PLL133, 40);
		} else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
		/* do nothing */
		} else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
		@@ -1263,11 +1279,11 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
		newbits2 = newbits1 \| CLOCK_CTRL_44MHZ_CORE;
		}

		tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl \| newbits1);
		udelay(40);
		tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl \| newbits1,
		40);

		tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl \| newbits2);
		udelay(40);
		tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl \| newbits2,
		40);

		if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
		u32 newbits3;
		@@ -1281,9 +1297,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
		newbits3 = CLOCK_CTRL_44MHZ_CORE;
		}

		tw32_f(TG3PCI_CLOCK_CTRL,
		tp->pci_clock_ctrl \| newbits3);
		udelay(40);
		tw32_wait_f(TG3PCI_CLOCK_CTRL,
		tp->pci_clock_ctrl \| newbits3, 40);
		}
		}

		@@ -1294,6 +1309,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
		tg3_writephy(tp, MII_TG3_EXT_CTRL,
		MII_TG3_EXT_CTRL_FORCE_LED_OFF);
		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
		tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
		}
		}
		@@ -7959,13 +7975,12 @@ static int tg3_test_memory(struct tg3 *tp)
		u32 offset;
		u32 len;
		} mem_tbl_570x[] = {
		{ 0x00000000, 0x01000},
		{ 0x00000000, 0x00b50},
		{ 0x00002000, 0x1c000},
		{ 0xffffffff, 0x00000}
		}, mem_tbl_5705[] = {
		{ 0x00000100, 0x0000c},
		{ 0x00000200, 0x00008},
		{ 0x00000b50, 0x00400},
		{ 0x00004000, 0x00800},
		{ 0x00006000, 0x01000},
		{ 0x00008000, 0x02000},
		@@ -10466,7 +10481,7 @@ static char * __devinit tg3_bus_string(struct tg3 tp, char str)
		return str;
		}

		static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
		static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
		{
		struct pci_dev *peer;
		unsigned int func, devnr = tp->pdev->devfn & ~7;
		@@ -10719,8 +10734,9 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
		tp->rx_pending = 63;
		}

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
		tp->pdev_peer = tg3_find_5704_peer(tp);
		if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) \|\|
		(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
		tp->pdev_peer = tg3_find_peer(tp);

		err = tg3_get_device_address(tp);
		if (err) {