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Commit 92bd1bf0 authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: HSW PM Frequency bits fix 



According to HSW PM programming guide, frequency bits starts at
24 instead of 25.

v2: Paulo Zanoni noticed that only frequency bits can be set at
GEN6_RPNSWREQ. All others are read only.

CC: Ben Widawsky <ben@bwidawsk.net>
CC: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a42f704b

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4190,6 +4190,7 @@ 
#define GEN6_RPNSWREQ				0xA008

#define   GEN6_TURBO_DISABLE			(1<<31)

#define   GEN6_FREQUENCY(x)			((x)<<25)

#define   HSW_FREQUENCY(x)			((x)<<24)

#define   GEN6_OFFSET(x)			((x)<<19)

#define   GEN6_AGGRESSIVE_TURBO			(0<<15)

#define GEN6_RC_VIDEO_FREQ			0xA00C

drivers/gpu/drm/i915/intel_pm.c

+21 −10
Original line number Diff line number Diff line
@@ -2460,6 +2460,10 @@ void gen6_set_rps(struct drm_device *dev, u8 val) 
	if (val == dev_priv->rps.cur_delay)

		return;



	if (IS_HASWELL(dev))

		I915_WRITE(GEN6_RPNSWREQ,

			   HSW_FREQUENCY(val));

	else

		I915_WRITE(GEN6_RPNSWREQ,

			   GEN6_FREQUENCY(val) |

			   GEN6_OFFSET(0) |
@@ -2601,12 +2605,19 @@ static void gen6_enable_rps(struct drm_device *dev) 
		   GEN6_RC_CTL_EI_MODE(1) |

		   GEN6_RC_CTL_HW_ENABLE);



	if (IS_HASWELL(dev)) {

		I915_WRITE(GEN6_RPNSWREQ,

			   HSW_FREQUENCY(10));

		I915_WRITE(GEN6_RC_VIDEO_FREQ,

			   HSW_FREQUENCY(12));

	} else {

		I915_WRITE(GEN6_RPNSWREQ,

			   GEN6_FREQUENCY(10) |

			   GEN6_OFFSET(0) |

			   GEN6_AGGRESSIVE_TURBO);

		I915_WRITE(GEN6_RC_VIDEO_FREQ,

			   GEN6_FREQUENCY(12));

	}



	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);

	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,