Documentation: arm: msm: Introduce L2 cache clock controller bindings

Take snapshot of L2 cache clock controller bindings
as of msm-3.10 commit: 91c38a689559d5f45b203a536429a0caa47d859e
(Merge "lpm-workarounds: queue work if perf cores are hotplugged").

Change-Id: I4319ed0a6fd5a488c8cff209be24afb3091b85a4
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>