Loading arch/arm64/include/asm/edac.h +8 −0 Original line number Diff line number Diff line Loading @@ -13,8 +13,16 @@ #ifndef ASM_EDAC_H #define ASM_EDAC_H #if defined(CONFIG_EDAC_CORTEX_ARM64) && \ !defined(CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY) void arm64_check_cache_ecc(void *info); #else static inline void arm64_check_cache_ecc(void *info) { } #endif static inline void atomic_scrub(void *addr, int size) { return; } #endif arch/arm64/kernel/smp.c +2 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,7 @@ #include <asm/sections.h> #include <asm/tlbflush.h> #include <asm/ptrace.h> #include <asm/edac.h> #define CREATE_TRACE_POINTS #include <trace/events/ipi.h> Loading Loading @@ -584,6 +585,7 @@ static void ipi_cpu_stop(unsigned int cpu, struct pt_regs *regs) pr_crit("CPU%u: stopping\n", cpu); show_regs(regs); dump_stack(); arm64_check_cache_ecc(NULL); raw_spin_unlock(&stop_lock); } Loading arch/arm64/kernel/traps.c +8 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,8 @@ #include <asm/stacktrace.h> #include <asm/exception.h> #include <asm/system_misc.h> #include <asm/esr.h> #include <asm/edac.h> #include <trace/events/exception.h> Loading Loading @@ -442,6 +444,12 @@ asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr) info.si_code = ILL_ILLOPC; info.si_addr = pc; if (esr >> ESR_EL1_EC_SHIFT == ESR_EL1_EC_SERROR) { pr_crit("System error detected. ESR.ISS = %08x\n", esr & 0xffffff); arm64_check_cache_ecc(NULL); } arm64_notify_die("Oops - bad mode", regs, &info, 0); } Loading arch/arm64/mm/fault.c +2 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,7 @@ #include <asm/system_misc.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> #include <asm/edac.h> #include <trace/events/exception.h> Loading Loading @@ -372,6 +373,7 @@ static int __kprobes do_translation_fault(unsigned long addr, */ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) { arm64_check_cache_ecc(NULL); return 1; } Loading Loading
arch/arm64/include/asm/edac.h +8 −0 Original line number Diff line number Diff line Loading @@ -13,8 +13,16 @@ #ifndef ASM_EDAC_H #define ASM_EDAC_H #if defined(CONFIG_EDAC_CORTEX_ARM64) && \ !defined(CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY) void arm64_check_cache_ecc(void *info); #else static inline void arm64_check_cache_ecc(void *info) { } #endif static inline void atomic_scrub(void *addr, int size) { return; } #endif
arch/arm64/kernel/smp.c +2 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,7 @@ #include <asm/sections.h> #include <asm/tlbflush.h> #include <asm/ptrace.h> #include <asm/edac.h> #define CREATE_TRACE_POINTS #include <trace/events/ipi.h> Loading Loading @@ -584,6 +585,7 @@ static void ipi_cpu_stop(unsigned int cpu, struct pt_regs *regs) pr_crit("CPU%u: stopping\n", cpu); show_regs(regs); dump_stack(); arm64_check_cache_ecc(NULL); raw_spin_unlock(&stop_lock); } Loading
arch/arm64/kernel/traps.c +8 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,8 @@ #include <asm/stacktrace.h> #include <asm/exception.h> #include <asm/system_misc.h> #include <asm/esr.h> #include <asm/edac.h> #include <trace/events/exception.h> Loading Loading @@ -442,6 +444,12 @@ asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr) info.si_code = ILL_ILLOPC; info.si_addr = pc; if (esr >> ESR_EL1_EC_SHIFT == ESR_EL1_EC_SERROR) { pr_crit("System error detected. ESR.ISS = %08x\n", esr & 0xffffff); arm64_check_cache_ecc(NULL); } arm64_notify_die("Oops - bad mode", regs, &info, 0); } Loading
arch/arm64/mm/fault.c +2 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,7 @@ #include <asm/system_misc.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> #include <asm/edac.h> #include <trace/events/exception.h> Loading Loading @@ -372,6 +373,7 @@ static int __kprobes do_translation_fault(unsigned long addr, */ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) { arm64_check_cache_ecc(NULL); return 1; } Loading