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Commit 91fc4cc0 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

perf, x86: Add new stalled cycles events for Intel and AMD CPUs 

Extend the Intel and AMD event definitions with generic front-end and
back-end stall events.

( These are only approximations - suggestions are welcome for better events. )

Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Link: http://lkml.kernel.org/n/tip-7y40wib8n001io7hjpn1dsrm@git.kernel.org


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 8f622422

arch/x86/kernel/cpu/perf_event_amd.c

+8 −6
Original line number Diff line number Diff line
@@ -102,6 +102,8 @@ static const u64 amd_perfmon_event_map[] = 
  [PERF_COUNT_HW_CACHE_MISSES]			= 0x0081,

  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]		= 0x00c2,

  [PERF_COUNT_HW_BRANCH_MISSES]			= 0x00c3,

  [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00d0, /* "Decoder empty" event */

  [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= 0x00d1, /* "Dispatch stalls" event */

};



static u64 amd_pmu_event_map(int hw_event)

arch/x86/kernel/cpu/perf_event_intel.c

+3 −1
Original line number Diff line number Diff line
@@ -1413,7 +1413,9 @@ static __init int intel_pmu_init(void) 
		x86_pmu.enable_all = intel_pmu_nhm_enable_all;

		x86_pmu.extra_regs = intel_nehalem_extra_regs;



		/* Install the stalled-cycles event: UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */

		/* UOPS_ISSUED.STALLED_CYCLES */

		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;

		/* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */

		intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;



		if (ebx & 0x40) {