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Commit 918d80a1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpu handling changes from Ingo Molnar:
 "Bigger changes:

   - Intel CPU hardware-enablement: new vector instructions support
     (AVX-512), by Fenghua Yu.

   - Support the clflushopt instruction and use it in appropriate
     places.  clflushopt is similar to clflush but with more relaxed
     ordering, by Ross Zwisler.

   - MSR accessor cleanups, by Borislav Petkov.

   - 'forcepae' boot flag for those who have way too much time to spend
     on way too old Pentium-M systems and want to live way too
     dangerously, by Chris Bainbridge"

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, cpu: Add forcepae parameter for booting PAE kernels on PAE-disabled Pentium M
  Rename TAINT_UNSAFE_SMP to TAINT_CPU_OUT_OF_SPEC
  x86, intel: Make MSR_IA32_MISC_ENABLE bit constants systematic
  x86, Intel: Convert to the new bit access MSR accessors
  x86, AMD: Convert to the new bit access MSR accessors
  x86: Add another set of MSR accessor functions
  x86: Use clflushopt in drm_clflush_virt_range
  x86: Use clflushopt in drm_clflush_page
  x86: Use clflushopt in clflush_cache_range
  x86: Add support for the clflushopt instruction
  x86, AVX-512: Enable AVX-512 States Context Switch
  x86, AVX-512: AVX-512 Feature Detection
parents 26a5c0df 69f2366c

Documentation/kernel-parameters.txt

+7 −0
Original line number Diff line number Diff line
@@ -1011,6 +1011,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 
			parameter will force ia64_sal_cache_flush to call

			ia64_pal_cache_flush instead of SAL_CACHE_FLUSH.



	forcepae [X86-32]

			Forcefully enable Physical Address Extension (PAE).

			Many Pentium M systems disable PAE but may have a

			functionally usable PAE implementation.

			Warning: use of this parameter will taint the kernel

			and may cause unknown problems.



	ftrace=[tracer]

			[FTRACE] will set and start the specified tracer

			as early as possible in order to facilitate early

arch/x86/boot/cpucheck.c

+20 −0
Original line number Diff line number Diff line
@@ -67,6 +67,13 @@ static int is_transmeta(void) 
	       cpu_vendor[2] == A32('M', 'x', '8', '6');

}



static int is_intel(void)

{

	return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&

	       cpu_vendor[1] == A32('i', 'n', 'e', 'I') &&

	       cpu_vendor[2] == A32('n', 't', 'e', 'l');

}



/* Returns a bitmask of which words we have error bits in */

static int check_cpuflags(void)

{
@@ -153,6 +160,19 @@ int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr) 
		asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));



		err = check_cpuflags();

	} else if (err == 0x01 &&

		   !(err_flags[0] & ~(1 << X86_FEATURE_PAE)) &&

		   is_intel() && cpu.level == 6 &&

		   (cpu.model == 9 || cpu.model == 13)) {

		/* PAE is disabled on this Pentium M but can be forced */

		if (cmdline_find_option_bool("forcepae")) {

			puts("WARNING: Forcing PAE in CPU flags\n");

			set_bit(X86_FEATURE_PAE, cpu.flags);

			err = check_cpuflags();

		}

		else {

			puts("WARNING: PAE disabled. Use parameter 'forcepae' to enable at your own risk!\n");

		}

	}



	if (err_flags_ptr)

arch/x86/include/asm/cpufeature.h

+5 −0
Original line number Diff line number Diff line
@@ -217,9 +217,14 @@ 
#define X86_FEATURE_INVPCID	(9*32+10) /* Invalidate Processor Context ID */

#define X86_FEATURE_RTM		(9*32+11) /* Restricted Transactional Memory */

#define X86_FEATURE_MPX		(9*32+14) /* Memory Protection Extension */

#define X86_FEATURE_AVX512F	(9*32+16) /* AVX-512 Foundation */

#define X86_FEATURE_RDSEED	(9*32+18) /* The RDSEED instruction */

#define X86_FEATURE_ADX		(9*32+19) /* The ADCX and ADOX instructions */

#define X86_FEATURE_SMAP	(9*32+20) /* Supervisor Mode Access Prevention */

#define X86_FEATURE_CLFLUSHOPT	(9*32+23) /* CLFLUSHOPT instruction */

#define X86_FEATURE_AVX512PF	(9*32+26) /* AVX-512 Prefetch */

#define X86_FEATURE_AVX512ER	(9*32+27) /* AVX-512 Exponential and Reciprocal */

#define X86_FEATURE_AVX512CD	(9*32+28) /* AVX-512 Conflict Detection */



/*

 * BUG word(s)

arch/x86/include/asm/msr.h

+2 −0
Original line number Diff line number Diff line
@@ -214,6 +214,8 @@ do { \ 


struct msr *msrs_alloc(void);

void msrs_free(struct msr *msrs);

int msr_set_bit(u32 msr, u8 bit);

int msr_clear_bit(u32 msr, u8 bit);



#ifdef CONFIG_SMP

int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);

arch/x86/include/asm/special_insns.h

+8 −0
Original line number Diff line number Diff line
@@ -191,6 +191,14 @@ static inline void clflush(volatile void *__p) 
	asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));

}



static inline void clflushopt(volatile void *__p)

{

	alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",

		       ".byte 0x66; clflush %P0",

		       X86_FEATURE_CLFLUSHOPT,

		       "+m" (*(volatile char __force *)__p));

}



#define nop() asm volatile ("nop")