Merge "Merge 'android-3.18.113' (f6efdb0) into 'msm-3.18'" (91750352) · Commits · e / devices / android_kernel_xiaomi_markw

Documentation/ABI/testing/sysfs-fs-f2fs

+1 −0

Original line number	Diff line number	Diff line
		@@ -101,6 +101,7 @@ Date: February 2015
		Contact: "Jaegeuk Kim" <jaegeuk@kernel.org>
		Description:
		Controls the trimming rate in batch mode.
		<deprecated>

		What: /sys/fs/f2fs/<disk>/cp_interval
		Date: October 2015

Documentation/device-mapper/thin-provisioning.txt

+5 −3

Original line number	Diff line number	Diff line
		@@ -112,9 +112,11 @@ $low_water_mark is expressed in blocks of size $data_block_size. If
		free space on the data device drops below this level then a dm event
		will be triggered which a userspace daemon should catch allowing it to
		extend the pool device. Only one such event will be sent.
		Resuming a device with a new table itself triggers an event so the
		userspace daemon can use this to detect a situation where a new table
		already exceeds the threshold.

		No special event is triggered if a just resumed device's free space is below
		the low water mark. However, resuming a device always triggers an
		event; a userspace daemon should verify that free space exceeds the low
		water mark when handling this event.

		A low water mark for the metadata device is maintained in the kernel and
		will trigger a dm event if free space on the metadata device drops below

Documentation/filesystems/f2fs.txt

+9 −7

Original line number	Diff line number	Diff line
		@@ -169,13 +169,15 @@ whint_mode=%s Control which write hints are passed down to block
		passes down hints with its policy.
		alloc_mode=%s Adjust block allocation policy, which supports "reuse"
		and "default".
		fsync_mode=%s Control the policy of fsync. Currently supports "posix"
		and "strict". In "posix" mode, which is default, fsync
		will follow POSIX semantics and does a light operation
		to improve the filesystem performance. In "strict" mode,
		fsync will be heavy and behaves in line with xfs, ext4
		and btrfs, where xfstest generic/342 will pass, but the
		performance will regress.
		fsync_mode=%s Control the policy of fsync. Currently supports "posix",
		"strict", and "nobarrier". In "posix" mode, which is
		default, fsync will follow POSIX semantics and does a
		light operation to improve the filesystem performance.
		In "strict" mode, fsync will be heavy and behaves in line
		with xfs, ext4 and btrfs, where xfstest generic/342 will
		pass, but the performance will regress. "nobarrier" is
		based on "posix", but doesn't issue flush command for
		non-atomic files likewise "nobarrier" mount option.
		test_dummy_encryption Enable dummy encryption, which provides a fake fscrypt
		context. The fake fscrypt context is used by xfstests.

Makefile

+1 −1

Original line number	Diff line number	Diff line
		VERSION = 3
		PATCHLEVEL = 18
		SUBLEVEL = 107
		SUBLEVEL = 113
		EXTRAVERSION =
		NAME = Diseased Newt

arch/alpha/include/asm/xchg.h

+22 −8

Original line number	Diff line number	Diff line
		@@ -11,6 +11,10 @@
		* Atomic exchange.
		* Since it can be used to implement critical sections
		* it must clobber "memory" (also for interrupts in UP).
		*
		* The leading and the trailing memory barriers guarantee that these
		* operations are fully ordered.
		*
		*/

		static inline unsigned long
		@@ -18,6 +22,7 @@ ____xchg(_u8, volatile char *m, unsigned long val)
		{
		unsigned long ret, tmp, addr64;

		smp_mb();
		__asm__ __volatile__(
		" andnot %4,7,%3\n"
		" insbl %1,%4,%1\n"
		@@ -42,6 +47,7 @@ ____xchg(_u16, volatile short *m, unsigned long val)
		{
		unsigned long ret, tmp, addr64;

		smp_mb();
		__asm__ __volatile__(
		" andnot %4,7,%3\n"
		" inswl %1,%4,%1\n"
		@@ -66,6 +72,7 @@ ____xchg(_u32, volatile int *m, unsigned long val)
		{
		unsigned long dummy;

		smp_mb();
		__asm__ __volatile__(
		"1: ldl_l %0,%4\n"
		" bis $31,%3,%1\n"
		@@ -86,6 +93,7 @@ ____xchg(_u64, volatile long *m, unsigned long val)
		{
		unsigned long dummy;

		smp_mb();
		__asm__ __volatile__(
		"1: ldq_l %0,%4\n"
		" bis $31,%3,%1\n"
		@@ -127,10 +135,12 @@ ____xchg(, volatile void *ptr, unsigned long x, int size)
		* store NEW in MEM. Return the initial value in MEM. Success is
		* indicated by comparing RETURN with OLD.
		*
		* The memory barrier should be placed in SMP only when we actually
		* make the change. If we don't change anything (so if the returned
		* prev is equal to old) then we aren't acquiring anything new and
		* we don't need any memory barrier as far I can tell.
		* The leading and the trailing memory barriers guarantee that these
		* operations are fully ordered.
		*
		* The trailing memory barrier is placed in SMP unconditionally, in
		* order to guarantee that dependency ordering is preserved when a
		* dependency is headed by an unsuccessful operation.
		*/

		static inline unsigned long
		@@ -138,6 +148,7 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
		{
		unsigned long prev, tmp, cmp, addr64;

		smp_mb();
		__asm__ __volatile__(
		" andnot %5,7,%4\n"
		" insbl %1,%5,%1\n"
		@@ -149,8 +160,8 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
		" or %1,%2,%2\n"
		" stq_c %2,0(%4)\n"
		" beq %2,3f\n"
		__ASM__MB
		"2:\n"
		__ASM__MB
		".subsection 2\n"
		"3: br 1b\n"
		".previous"
		@@ -165,6 +176,7 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
		{
		unsigned long prev, tmp, cmp, addr64;

		smp_mb();
		__asm__ __volatile__(
		" andnot %5,7,%4\n"
		" inswl %1,%5,%1\n"
		@@ -176,8 +188,8 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
		" or %1,%2,%2\n"
		" stq_c %2,0(%4)\n"
		" beq %2,3f\n"
		__ASM__MB
		"2:\n"
		__ASM__MB
		".subsection 2\n"
		"3: br 1b\n"
		".previous"
		@@ -192,6 +204,7 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
		{
		unsigned long prev, cmp;

		smp_mb();
		__asm__ __volatile__(
		"1: ldl_l %0,%5\n"
		" cmpeq %0,%3,%1\n"
		@@ -199,8 +212,8 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
		" mov %4,%1\n"
		" stl_c %1,%2\n"
		" beq %1,3f\n"
		__ASM__MB
		"2:\n"
		__ASM__MB
		".subsection 2\n"
		"3: br 1b\n"
		".previous"
		@@ -215,6 +228,7 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
		{
		unsigned long prev, cmp;

		smp_mb();
		__asm__ __volatile__(
		"1: ldq_l %0,%5\n"
		" cmpeq %0,%3,%1\n"
		@@ -222,8 +236,8 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
		" mov %4,%1\n"
		" stq_c %1,%2\n"
		" beq %1,3f\n"
		__ASM__MB
		"2:\n"
		__ASM__MB
		".subsection 2\n"
		"3: br 1b\n"
		".previous"