Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9134c40b authored by Srinu Gorle's avatar Srinu Gorle
Browse files

ARM: dts: msm: update DCVS macro blocks per frame value for msmtitanium 



As macro blocks per frame is incorrect, DCVS is never getting kicked-in.
Updating MB's per frame entry for DCVS algorithm as per actual resolution
instead of venus aligned resolution.

CRs-Fixed: 970253
Change-Id: I2342df306c38ee2b5d130c87d68ee5d4c614783f
Signed-off-by: default avatarSrinu Gorle <sgorle@codeaurora.org>
parent 74240891

arch/arm/boot/dts/qcom/msmtitanium-vidc.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -46,8 +46,8 @@ 
			/* Enc UHD@30 H.264/HEVC Nom+ to Turbo */

			<432000 432000 972000 0x4000004>;

		qcom,dcvs-limit =

			<32640 30>, /* Encoder UHD */

			<32640 30>; /* Decoder UHD */

			<32400 30>, /* Encoder UHD */

			<32400 30>; /* Decoder UHD */

		qcom,allowed-clock-rates = <465000000 400000000

			360000000 310000000 228570000 114290000>;

		qcom,clock-freq-tbl {