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Commit 9106c410 authored by Or Gerlitz's avatar Or Gerlitz Committed by Roland Dreier
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IB/mlx4: Fix SL to 802.1Q priority-bits mapping for IBoE 



For IBoE, SLs 0-7 are mapped to Ethernet 802.1Q user priority bits
(pbits) which are part of the VLAN tag, SLs 8-15 are reserved.

Under Ethernet, the ConnectX firmware treats (decode/encode) the four
bit SL field in various constructs such as QPC / UD WQE / CQE as PPP0
and not as 0PPP. This correlates well to the fact that within the
vlan tag the pbits are located in bits 15-13 and not 12-14.

The current code wasn't consistent around that area - the
encoding was correct for the IBoE QPC.path.schedule_queue field,
but was wrong for IBoE CQEs and when MLX header was built.

These inconsistencies resulted in wrong SL <--> wire 802.1Q pbits
mapping, which is fixed by using SL <--> PPP0 all around the place.

Signed-off-by: default avatarOren Duer <oren@mellanox.co.il>
Signed-off-by: default avatarOr Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: default avatarRoland Dreier <roland@purestorage.com>
parent 5f0a6e2d

drivers/infiniband/hw/mlx4/ah.c

+1 −1
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@ static struct ib_ah *create_iboe_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr 
		ah->av.ib.dlid = cpu_to_be16(0xc000);



	memcpy(ah->av.eth.dgid, ah_attr->grh.dgid.raw, 16);

	ah->av.eth.sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 28);

	ah->av.eth.sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 29);



	return &ah->ibah;

}

drivers/infiniband/hw/mlx4/cq.c

+5 −1
Original line number Diff line number Diff line
@@ -715,13 +715,17 @@ repoll: 
		}



		wc->slid	   = be16_to_cpu(cqe->rlid);

		wc->sl		   = be16_to_cpu(cqe->sl_vid) >> 12;

		g_mlpath_rqpn	   = be32_to_cpu(cqe->g_mlpath_rqpn);

		wc->src_qp	   = g_mlpath_rqpn & 0xffffff;

		wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;

		wc->wc_flags	  |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;

		wc->pkey_index     = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;

		wc->csum_ok	   = mlx4_ib_ipoib_csum_ok(cqe->status, cqe->checksum);

		if (rdma_port_get_link_layer(wc->qp->device,

				(*cur_qp)->port) == IB_LINK_LAYER_ETHERNET)

			wc->sl  = be16_to_cpu(cqe->sl_vid) >> 13;

		else

			wc->sl  = be16_to_cpu(cqe->sl_vid) >> 12;

	}



	return 0;

drivers/infiniband/hw/mlx4/qp.c

+2 −2
Original line number Diff line number Diff line
@@ -962,7 +962,7 @@ static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah, 


	if (is_eth) {

		path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |

			((port - 1) << 6) | ((ah->sl & 7) << 3) | ((ah->sl & 8) >> 1);

			((port - 1) << 6) | ((ah->sl & 7) << 3);



		if (!(ah->ah_flags & IB_AH_GRH))

			return -1;
@@ -1437,7 +1437,7 @@ static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr, 
			u16 pcp;



			sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);

			pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 27 & 3) << 13;

			pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;

			sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);

		}

	} else {