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Commit 90e93648 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm 

* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: pm: avoid writing the auxillary control register for ARMv7
  ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
  ARM: pm: arm920/926: fix number of registers saved
  ARM: pm: CPU specific code should not overwrite r1 (v:p offset)
  ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU
  ARM: 7065/1: kexec: ensure new kernel is entered in ARM state
  ARM: 7003/1: vexpress: Add clock definition for the SP805.
  ARM: 7051/1: cpuimx* boards: fix mach-types errors
  ARM: 7019/1: Footbridge: select CLKEVT_I8253 for ARCH_NETWINDER
  ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled
  ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.
  ARM: 6967/1: ep93xx: ts72xx: fix board model detection
  ARM: 6965/1: ep93xx: add model detection for ts-7300 and ts-7400 boards
  ARM: cache: detect VIPT aliasing I-cache on ARMv6
  ARM: twd: register clockevents device before enabling PPI
  ARM: realview: ensure visibility of writes during reset
  ARM: perf: make name of arm_pmu_type consistent
  ARM: perf: fix prototype of release_pmu
  ARM: fix perf build with uclibc toolchains
parents 3ae627b5 25904157

arch/arm/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -1271,6 +1271,18 @@ config ARM_ERRATA_754327 
	  This workaround defines cpu_relax() as smp_mb(), preventing correctly

	  written polling loops from denying visibility of updates to memory.



config ARM_ERRATA_364296

	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"

	depends on CPU_V6 && !SMP

	help

	  This options enables the workaround for the 364296 ARM1136

	  r0p2 erratum (possible cache data corruption with

	  hit-under-miss enabled). It sets the undocumented bit 31 in

	  the auxiliary control register and the FI bit in the control

	  register, thus disabling hit-under-miss without putting the

	  processor into full low interrupt latency mode. ARM11MPCore

	  is not affected.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/include/asm/hardware/cache-l2x0.h

+1 −1
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ 
#define L2X0_AUX_CTRL_MASK			0xc0000fff

#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT	16

#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT		17

#define L2X0_AUX_CTRL_WAY_SIZE_MASK		(0x3 << 17)

#define L2X0_AUX_CTRL_WAY_SIZE_MASK		(0x7 << 17)

#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT	22

#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT		26

#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT		27

arch/arm/include/asm/pmu.h

+5 −5
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ struct arm_pmu_platdata { 
 * encoded error on failure.

 */

extern struct platform_device *

reserve_pmu(enum arm_pmu_type device);

reserve_pmu(enum arm_pmu_type type);



/**

 * release_pmu() - Relinquish control of the performance counters
@@ -62,26 +62,26 @@ release_pmu(enum arm_pmu_type type); 
 * the actual hardware initialisation.

 */

extern int

init_pmu(enum arm_pmu_type device);

init_pmu(enum arm_pmu_type type);



#else /* CONFIG_CPU_HAS_PMU */



#include <linux/err.h>



static inline struct platform_device *

reserve_pmu(enum arm_pmu_type device)

reserve_pmu(enum arm_pmu_type type)

{

	return ERR_PTR(-ENODEV);

}



static inline int

release_pmu(struct platform_device *pdev)

release_pmu(enum arm_pmu_type type)

{

	return -ENODEV;

}



static inline int

init_pmu(enum arm_pmu_type device)

init_pmu(enum arm_pmu_type type)

{

	return -ENODEV;

}

arch/arm/kernel/pmu.c

+13 −13
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ static int __devinit pmu_register(struct platform_device *pdev, 
{

	if (type < 0 || type >= ARM_NUM_PMU_DEVICES) {

		pr_warning("received registration request for unknown "

				"device %d\n", type);

				"PMU device type %d\n", type);

		return -EINVAL;

	}
@@ -112,17 +112,17 @@ static int __init register_pmu_driver(void) 
device_initcall(register_pmu_driver);



struct platform_device *

reserve_pmu(enum arm_pmu_type device)

reserve_pmu(enum arm_pmu_type type)

{

	struct platform_device *pdev;



	if (test_and_set_bit_lock(device, &pmu_lock)) {

	if (test_and_set_bit_lock(type, &pmu_lock)) {

		pdev = ERR_PTR(-EBUSY);

	} else if (pmu_devices[device] == NULL) {

		clear_bit_unlock(device, &pmu_lock);

	} else if (pmu_devices[type] == NULL) {

		clear_bit_unlock(type, &pmu_lock);

		pdev = ERR_PTR(-ENODEV);

	} else {

		pdev = pmu_devices[device];

		pdev = pmu_devices[type];

	}



	return pdev;
@@ -130,11 +130,11 @@ reserve_pmu(enum arm_pmu_type device) 
EXPORT_SYMBOL_GPL(reserve_pmu);



int

release_pmu(enum arm_pmu_type device)

release_pmu(enum arm_pmu_type type)

{

	if (WARN_ON(!pmu_devices[device]))

	if (WARN_ON(!pmu_devices[type]))

		return -EINVAL;

	clear_bit_unlock(device, &pmu_lock);

	clear_bit_unlock(type, &pmu_lock);

	return 0;

}

EXPORT_SYMBOL_GPL(release_pmu);
@@ -182,17 +182,17 @@ init_cpu_pmu(void) 
}



int

init_pmu(enum arm_pmu_type device)

init_pmu(enum arm_pmu_type type)

{

	int err = 0;



	switch (device) {

	switch (type) {

	case ARM_PMU_DEVICE_CPU:

		err = init_cpu_pmu();

		break;

	default:

		pr_warning("attempt to initialise unknown device %d\n",

				device);

		pr_warning("attempt to initialise PMU of unknown "

			   "type %d\n", type);

		err = -EINVAL;

	}

arch/arm/kernel/relocate_kernel.S

+2 −1
Original line number Diff line number Diff line
@@ -57,7 +57,8 @@ relocate_new_kernel: 
	mov r0,#0

	ldr r1,kexec_mach_type

	ldr r2,kexec_boot_atags

	mov pc,lr

 ARM(	mov pc, lr	)

 THUMB(	bx lr		)



	.align