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Commit 90c540cd authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "mmc: sdhci-msm: Correct the CDR toggle logic"

parents f7ce0a1c d2ad7697

drivers/mmc/host/sdhci-msm.c

+11 −8
Original line number Diff line number Diff line
@@ -2364,14 +2364,17 @@ static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type) 


static void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable)

{

	if (enable)

		writel_relaxed((readl_relaxed(host->ioaddr +

					      CORE_DLL_CONFIG) | CORE_CDR_EN),

			       host->ioaddr + CORE_DLL_CONFIG);

	else

		writel_relaxed((readl_relaxed(host->ioaddr +

					      CORE_DLL_CONFIG) & ~CORE_CDR_EN),

			       host->ioaddr + CORE_DLL_CONFIG);

	u32 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);



	if (enable) {

		config |= CORE_CDR_EN;

		config &= ~CORE_CDR_EXT_EN;

		writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);

	} else {

		config &= ~CORE_CDR_EN;

		config |= CORE_CDR_EXT_EN;

		writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);

	}

}



static unsigned int sdhci_msm_max_segs(void)

drivers/mmc/host/sdhci.c

+8 −2
Original line number Diff line number Diff line
@@ -1070,9 +1070,15 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, 


	if (data->flags & MMC_DATA_READ) {

		mode |= SDHCI_TRNS_READ;

		if (host->ops->toggle_cdr)

		if (host->ops->toggle_cdr) {

			if ((cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) ||

				(cmd->opcode == MMC_SEND_TUNING_BLOCK_HS400) ||

				(cmd->opcode == MMC_SEND_TUNING_BLOCK))

				host->ops->toggle_cdr(host, false);

			else

				host->ops->toggle_cdr(host, true);

		}

	}

	if (host->ops->toggle_cdr && (data->flags & MMC_DATA_WRITE))

		host->ops->toggle_cdr(host, false);

	if (host->flags & SDHCI_REQ_USE_DMA)

include/uapi/linux/mmc/mmc.h

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#define MMC_READ_MULTIPLE_BLOCK  18   /* adtc [31:0] data addr   R1  */

#define MMC_SEND_TUNING_BLOCK    19   /* adtc                    R1  */

#define MMC_SEND_TUNING_BLOCK_HS200	21	/* adtc R1  */

#define MMC_SEND_TUNING_BLOCK_HS400      MMC_SEND_TUNING_BLOCK_HS200



#define MMC_TUNING_BLK_PATTERN_4BIT_SIZE	 64

#define MMC_TUNING_BLK_PATTERN_8BIT_SIZE	128