Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8fb303c7 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] SB1250: Fix bugs/warnings by creative use of volatile. 



Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 41a8198f

arch/mips/mm/pg-sb1.c

+1 −2
Original line number Diff line number Diff line
@@ -218,8 +218,7 @@ void sb1_dma_init(void) 
	for (i = 0; i < DM_NUM_CHANNELS; i++) {

		const u64 base_val = CPHYSADDR(&page_descr[i]) |

				     V_DM_DSCR_BASE_RINGSZ(1);

		volatile void *base_reg =

			IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));

		void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));



		__raw_writeq(base_val, base_reg);

		__raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);

arch/mips/pci/pci-bcm1480.c

+1 −1
Original line number Diff line number Diff line
@@ -216,7 +216,7 @@ static int __init bcm1480_pcibios_init(void) 
	/*

	 * See if the PCI bus has been configured by the firmware.

	 */

	reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));

	reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));

	if (!(reg & M_BCM1480_SYS_PCI_HOST)) {

		bcm1480_bus_status |= PCI_DEVICE_MODE;

	} else {

arch/mips/pci/pci-sb1250.c

+1 −1
Original line number Diff line number Diff line
@@ -228,7 +228,7 @@ static int __init sb1250_pcibios_init(void) 
	/*

	 * See if the PCI bus has been configured by the firmware.

	 */

	reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));

	reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));

	if (!(reg & M_SYS_PCI_HOST)) {

		sb1250_bus_status |= PCI_DEVICE_MODE;

	} else {

arch/mips/sibyte/bcm1480/smp.c

+3 −3
Original line number Diff line number Diff line
@@ -34,21 +34,21 @@ extern void smp_call_function_interrupt(void); 
 * independent of board/firmware

 */



static volatile void *mailbox_0_set_regs[] = {

static void *mailbox_0_set_regs[] = {

	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

	IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),

};



static volatile void *mailbox_0_clear_regs[] = {

static void *mailbox_0_clear_regs[] = {

	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

	IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),

};



static volatile void *mailbox_0_regs[] = {

static void *mailbox_0_regs[] = {

	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),

	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),

	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),

arch/mips/sibyte/swarm/setup.c

+10 −8
Original line number Diff line number Diff line
@@ -169,17 +169,19 @@ void __init plat_mem_setup(void) 
#define LEDS_PHYS MLEDS_PHYS

#endif



#define setled(index, c) \

  ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c)

void setleds(char *str)

{

	void *reg;

	int i;



	for (i = 0; i < 4; i++) {

		if (!str[i]) {

			setled(i, ' ');

		} else {

			setled(i, str[i]);

		}

		reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3);



		if (!str[i])

			writeb(' ', reg);

		else

			writeb(str[i], reg);

	}

}

#endif
 


#endif /* LEDS_PHYS */