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Commit 8d82f219 authored by Eric Benard's avatar Eric Benard Committed by David S. Miller
Browse files

net: fsl: fec: handle 10Mbps speed in RMII mode 



when the link is 10 Mbps and the mode is RMII, it's necessary
to set FRCONT to 1 in MIIGSK_CFGR to divide the RMII source
clock by 10 in order to support 10 Mbps operations.

Signed-off-by: default avatarEric Bénard <eric@eukrea.com>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 25cecd7e

drivers/net/ethernet/freescale/fec.c

+6 −3
Original line number Diff line number Diff line
@@ -476,6 +476,7 @@ fec_restart(struct net_device *ndev, int duplex) 
	} else {

#ifdef FEC_MIIGSK_ENR

		if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {

			u32 cfgr;

			/* disable the gasket and wait */

			writel(0, fep->hwp + FEC_MIIGSK_ENR);

			while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
@@ -486,9 +487,11 @@ fec_restart(struct net_device *ndev, int duplex) 
			 *   RMII, 50 MHz, no loopback, no echo

			 *   MII, 25 MHz, no loopback, no echo

			 */

			writel((fep->phy_interface == PHY_INTERFACE_MODE_RMII) ?

					1 : 0, fep->hwp + FEC_MIIGSK_CFGR);



			cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)

				? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;

			if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)

				cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;

			writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);



			/* re-enable the gasket */

			writel(2, fep->hwp + FEC_MIIGSK_ENR);

drivers/net/ethernet/freescale/fec.h

+4 −0
Original line number Diff line number Diff line
@@ -47,6 +47,10 @@ 
#define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */

#define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */



#define BM_MIIGSK_CFGR_MII		0x00

#define BM_MIIGSK_CFGR_RMII		0x01

#define BM_MIIGSK_CFGR_FRCONT_10M	0x40



#else



#define FEC_ECNTRL		0x000 /* Ethernet control reg */