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Commit 8d7db774 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add SDHC2 support for msmtitanium"

parents d2ee510b 9dade566

arch/arm/boot/dts/qcom/msmtitanium-cdp.dtsi

+57 −0
Original line number Diff line number Diff line
@@ -22,3 +22,60 @@ 
	pinctrl-0 = <&uart_console_active>;

};



&sdhc_1 {

	/* device core power supply */

	vdd-supply = <&pmtitanium_l8>;

	qcom,vdd-voltage-level = <2900000 2900000>;

	qcom,vdd-current-level = <200 570000>;



	/* device communication power supply */

	vdd-io-supply = <&pmtitanium_l5>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <200 325000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on  &sdc1_rclk_on>;

	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;



	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000

								384000000>;

	qcom,nonremovable;

	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";



	status = "ok";

};



&sdhc_2 {

	/* device core power supply */

	vdd-supply = <&pmtitanium_l11>;

	qcom,vdd-voltage-level = <2950000 2950000>;

	qcom,vdd-current-level = <15000 800000>;



	/* device communication power supply */

	vdd-io-supply = <&pmtitanium_l12>;

	qcom,vdd-io-voltage-level = <1800000 2950000>;

	qcom,vdd-io-current-level = <200 22000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;

	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;



	#address-cells = <0>;

	interrupt-parent = <&sdhc_2>;

	interrupts = <0 1 2>;

	#interrupt-cells = <1>;

	interrupt-map-mask = <0xffffffff>;

	interrupt-map = <0 &intc 0 125 0

		1 &intc 0 221 0

		2 &tlmm 133 0>;

	interrupt-names = "hc_irq", "pwr_irq", "status_irq";

	cd-gpios = <&tlmm 133 0x1>;



	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000

								192000000>;

	qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";



	status = "ok";

};

arch/arm/boot/dts/qcom/msmtitanium-mtp.dtsi

+57 −0
Original line number Diff line number Diff line
@@ -22,3 +22,60 @@ 
	pinctrl-0 = <&uart_console_active>;

};



&sdhc_1 {

	/* device core power supply */

	vdd-supply = <&pmtitanium_l8>;

	qcom,vdd-voltage-level = <2900000 2900000>;

	qcom,vdd-current-level = <200 570000>;



	/* device communication power supply */

	vdd-io-supply = <&pmtitanium_l5>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <200 325000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on  &sdc1_rclk_on>;

	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;



	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000

								384000000>;

	qcom,nonremovable;

	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";



	status = "ok";

};



&sdhc_2 {

	/* device core power supply */

	vdd-supply = <&pmtitanium_l11>;

	qcom,vdd-voltage-level = <2950000 2950000>;

	qcom,vdd-current-level = <15000 800000>;



	/* device communication power supply */

	vdd-io-supply = <&pmtitanium_l12>;

	qcom,vdd-io-voltage-level = <1800000 2950000>;

	qcom,vdd-io-current-level = <200 22000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;

	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;



	#address-cells = <0>;

	interrupt-parent = <&sdhc_2>;

	interrupts = <0 1 2>;

	#interrupt-cells = <1>;

	interrupt-map-mask = <0xffffffff>;

	interrupt-map = <0 &intc 0 125 0

		1 &intc 0 221 0

		2 &tlmm 133 0>;

	interrupt-names = "hc_irq", "pwr_irq", "status_irq";

	cd-gpios = <&tlmm 133 0x1>;



	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000

								192000000>;

	qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";



	status = "ok";

};

arch/arm/boot/dts/qcom/msmtitanium-pinctrl.dtsi

+88 −0
Original line number Diff line number Diff line
@@ -126,6 +126,94 @@ 
			};

		};



		sdc1_rclk_on: sdc1_rclk_on {

			config {

				pins = "sdc1_rclk";

				bias-pull-down; /* pull down */

			};

		};



		sdc1_rclk_off: sdc1_rclk_off {

			config {

				pins = "sdc1_rclk";

				bias-pull-down; /* pull down */

			};

		};



		sdc2_clk_on: sdc2_clk_on {

			config {

				pins = "sdc2_clk";

				drive-strength = <16>; /* 16 MA */

				bias-disable; /* NO pull */

			};

		};



		sdc2_clk_off: sdc2_clk_off {

			config {

				pins = "sdc2_clk";

				bias-disable; /* NO pull */

				drive-strength = <2>; /* 2 MA */

			};

		};



		sdc2_cmd_on: sdc2_cmd_on {

			config {

				pins = "sdc2_cmd";

				bias-pull-up; /* pull up */

				drive-strength = <10>; /* 10 MA */

			};

		};



		sdc2_cmd_off: sdc2_cmd_off {

			config {

				pins = "sdc2_cmd";

				bias-pull-up; /* pull up */

				drive-strength = <2>; /* 2 MA */

			};

		};



		sdc2_data_on: sdc2_data_on {

			config {

				pins = "sdc2_data";

				bias-pull-up; /* pull up */

				drive-strength = <10>; /* 10 MA */

			};

		};



		sdc2_data_off: sdc2_data_off {

			config {

				pins = "sdc2_data";

				bias-pull-up; /* pull up */

				drive-strength = <2>; /* 2 MA */

			};

		};



		sdc2_cd_on: cd_on {

			mux {

				pins = "gpio133";

				function = "gpio";

			};



			config {

				pins = "gpio133";

				drive-strength = <2>;

				bias-pull-up;

			};

		};



		sdc2_cd_off: cd_off {

			mux {

				pins = "gpio133";

				function = "gpio";

			};



			config {

				pins = "gpio133";

				drive-strength = <2>;

				bias-disable;

			};

		};



		i2c_2 {

			i2c_2_active: i2c_2_active {

				/* active state */

arch/arm/boot/dts/qcom/msmtitanium.dtsi

+57 −5
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ 
		smd21 = &smdtty_data21;

		smd36 = &smdtty_loopback;

		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */

		sdhc2 = &sdhc_2; /* SDC2 for SD card */

		i2c2 = &i2c_2;

		i2c5 = &i2c_5;

		spi3 = &spi_3;
@@ -1154,17 +1155,23 @@ 


	sdhc_1: sdhci@7824900 {

		compatible = "qcom,sdhci-msm";

		reg = <0x7824900 0x500>, <0x7824000 0x800>;

		reg-names = "hc_mem", "core_mem";

		reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>;

		reg-names = "hc_mem", "core_mem", "cmdq_mem";



		interrupts = <0 123 0>, <0 138 0>;

		interrupt-names = "hc_irq", "pwr_irq";



		qcom,bus-width = <8>;



		qcom,devfreq,freq-table = <52000000 200000000>;

		qcom,devfreq,freq-table = <50000000 200000000>;



		qcom,pm-qos-irq-type = "affine_irq";

		qcom,pm-qos-irq-latency = <2 200>;



		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-cmdq-latency-us = <2 200>, <2 200>;



		qcom,cpu-dma-latency-us = <60 340 900>;

		qcom,pm-qos-legacy-latency-us = <2 200>, <2 200>;



		qcom,msm-bus,name = "sdhc1";

		qcom,msm-bus,num-cases = <9>;
@@ -1182,8 +1189,53 @@ 
			100000000 200000000 400000000 4294967295>;



		clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>;

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>,

			 <&clock_gcc clk_gcc_sdcc1_ice_core_clk>;

		clock-names = "iface_clk", "core_clk", "ice_core_clk";

		qcom,ice-clk-rates = <270000000 160000000>;

		qcom,large-address-bus;



		status = "disabled";

	};



	sdhc_2: sdhci@7864900 {

		compatible = "qcom,sdhci-msm";

		reg = <0x7864900 0x500>, <0x7864000 0x800>;

		reg-names = "hc_mem", "core_mem";



		interrupts = <0 125 0>, <0 221 0>;

		interrupt-names = "hc_irq", "pwr_irq";



		qcom,bus-width = <4>;



		qcom,pm-qos-irq-type = "affine_irq";

		qcom,pm-qos-irq-latency = <2 200>;



		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-legacy-latency-us = <2 200>, <2 200>;



		qcom,devfreq,freq-table = <50000000 200000000>;



		qcom,msm-bus,name = "sdhc2";

		qcom,msm-bus,num-cases = <8>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */

			<81 512 1046 3200>,    /* 400 KB/s*/

			<81 512 52286 160000>, /* 20 MB/s */

			<81 512 65360 200000>, /* 25 MB/s */

			<81 512 130718 400000>, /* 50 MB/s */

			<81 512 261438 800000>, /* 100 MB/s */

			<81 512 261438 800000>, /* 200 MB/s */

			<81 512 1338562 4096000>; /* Max. bandwidth */

		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000

			100000000 200000000 400000000 4294967295>;



		clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,

			<&clock_gcc clk_gcc_sdcc2_apps_clk>;

		clock-names = "iface_clk", "core_clk";



		qcom,large-address-bus;

		status = "disabled";

	};



	spmi_bus: qcom,spmi@200f000 {