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Commit 8c7b72f2 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Remove WaFbcDisableDpfcClockGating on HSW 



Production HSW does not need it. I confirmed this with Art.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a74b0c48

drivers/gpu/drm/i915/i915_reg.h

+0 −3
Original line number Diff line number Diff line
@@ -1106,9 +1106,6 @@ 
					     _HSW_PIPE_SLICE_CHICKEN_1_A, + \

					     _HSW_PIPE_SLICE_CHICKEN_1_B)



#define HSW_CLKGATE_DISABLE_PART_1	0x46500

#define   HSW_DPFC_GATING_DISABLE	(1<<23)



/*

 * GPIO regs

 */

drivers/gpu/drm/i915/intel_pm.c

+0 −10
Original line number Diff line number Diff line
@@ -254,12 +254,6 @@ static void ironlake_disable_fbc(struct drm_device *dev) 
		dpfc_ctl &= ~DPFC_CTL_EN;

		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);



		if (IS_HASWELL(dev))

			/* WaFbcDisableDpfcClockGating:hsw */

			I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,

				   I915_READ(HSW_CLKGATE_DISABLE_PART_1) &

				   ~HSW_DPFC_GATING_DISABLE);



		DRM_DEBUG_KMS("disabled FBC\n");

	}

}
@@ -293,10 +287,6 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
		/* WaFbcAsynchFlipDisableFbcQueue:hsw */

		I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),

			   HSW_BYPASS_FBC_QUEUE);

		/* WaFbcDisableDpfcClockGating:hsw */

		I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,

			   I915_READ(HSW_CLKGATE_DISABLE_PART_1) |

			   HSW_DPFC_GATING_DISABLE);

	}



	I915_WRITE(SNB_DPFC_CTL_SA,